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ADC3664: Design Help

SVJS
Prodigy 140 points
Part Number: ADC3664

Designing the ADC3664 with Ultrascale FPGA. 

Doubt regarding following signals, need 100ohm termination in FPGA side or not?

DCLKP : Positive differential serial LVDS bit clock output.
DCLKM : Negative differential serial LVDS bit clock output.
FCLKP  : Positive differential serial LVDS frame clock output.
FCLKM : differential serial LVDS frame clock output.

  • 0
    TI__Mastermind 22030 points

    Hi SVJS,

    These clocks must be 100 ohm terminated. I suggest to verify whether the FPGA is capable of providing an internal 100 ohm termination. If the FPGA is unable then your design will need to include 100ohm differential resistors for terminating the clock pairs. You can also include these resistor footprints in your PCB but not populate the component so you have options.

    Regards, Chase