ADS8584S: ADS8584s

Hi Shalini,

The data conversion is initiated by the CONVSTA/B signals on ADS8584S which are controlled by your CPU or FPGA, so the actual ADC sampling rate is determined by the cycle time of your CONVSTA/B signals, please see the timing below:

Unfortunately, we do not have a sample Verilog code. However, please feel free to contact us if you have any questions about this ADC, thanks.

Regards,

Dale

Hi Shalini,

I've not received any response since my last answer to your question 25 days ago. I noticed you rejected my answer to close this thread. Do you still have any questions about ADS8584S ADC?

Regards,

Dale

The thread was closed. You can post a new query if you still have any questions about tADS8584S.