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ADS8353-Q1: SPI SDO data launch edge

Part Number: ADS8353-Q1

hello there, 

my test result of SPI SDO data latched edge is opposite with the datasheet. 

my test shows that the SDO latch edge is the rising edge of SCLK. 

however, the datasheet(figure 7-7. and table 10) say that the latch edge is falling edge. 

please let me the root cause of this issue.

BRs,

Shubiao Wang

  • Hi Shubiao,

    Can you please provide your SCLK frequency as well as how you are operating the device? Details on the device configuration will be helpful. Also, if you can provide a schematic, that would be great!

    Regards,
    Aaron Estrada

  • Aaron,

    Please refer to my SCH and configuration, please help me understand why  SPI mode of MISO I tested is different with data sheet?

    please help to clarify the SPI mode for both MISO and MOSI.

    SLCK is 8Mhz

    the reg configuration is shown below.

    0x86,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00

    Only the three bit is set, all the others are kept default.  

       

        SCH 

        

  • Hi Shubiao,

    Thanks for providing the additional details. Taking a look back at the scope capture you provided, I see that SCLK is being intermittently provided in bursts of 8clk cycles. Why is this? Can you provide a constant SCLK from CS falling edge to CS rising edge?

    Regards,
    Aaron