Hi,
I would like to get some information about timing accuracy for sampling time of this ADC. We are using this part for an application where having 100kHz sample rate is sufficient, but we have tighter requirement on sampling time instance. We have a 100kHz reference clock in the system and we can generate the "CS" signal from this clock with good accuracy. But we don't know how accurately the ADC generates its internal sampling signal (that opens the sampling switch) from the CS. For example is is possible the sampling will happen with >100ns latency after receiving the CS, or is the latency much lower than this?
I would really appreciate it if you could provide some information about this.
Thanks,
Behnam
