DAC7565: cannot be reset

Hello Yang, 

Just to confirm a few things: 

Is your VrefL connected to the ground? 

What are the states of LDAC and ENABLE pins? 

Try to give the device a command through SPI, does it give you any response in output? 

Thank you.

Illia V.

Vref is connected to the ground,

LDAC is always kept low, ENABLE is only pulled low when using SPI communication，

When I send a message to the device via SPI, there is a response on the output，
it will reset to 1.25V.

Hello Yang, 

Thank you for information. 

All of the connections and signals seem to be fine. 

I will try to recreate your circuit in lab. In the meantime do you have another device you could potentially swap to and check if the problem persists with a different device? 

Yes, I have this problem on two different devices.

there is a key message，touching the reset signal line with the ground wire can reset it, but can not be reset by using software to pull low.

and I want to ask，The reset signal is level-triggered, not edge-triggered, right?

Hello Yang, 

Let me ask you a few more follow up questions that might help me with debugging:

Where are the measurements that are shown on oscilloscope taken, are they taken directly on the pin or elsewhere? If there were taken elsewhere could you redo the measurement but check the output directly at the pin.

When you mentioned touching the reset signal with ground wire, where is this ground wire coming from? 

Do you have a unified ground between your device and controller? If no, please try to connect both devices to the same ground and try again. 

To answer your question, the reset signal is level-triggered. 

Thank you, 

Illia Volkov 

yes, the measurement are directly at the pin, when I mention touching the reset signal with ground wire, this ground wire is coming from DAC.

I don't have a unified ground between my device and controller, because there is optocoupler isolation between  the device and controller，

the two grounds are isolated.

Hello Yang, 

And just to make sure I understand it correctly, the first screenshot ( the one on the left) is the reading of the input to reset pin from your external reference? 

yes.

and I want to say, 

Whether the reset signal has a falling edge requirement？The falling edge time of the reset signal is about 10ns,You can read 
in the first screenshot ( the one on the right) 

Whether the reset signal conflicts with SPI communication，I don't care whether SPI communication is in progress when I reset, 
which means that SPI communication is still in progress during reset, will this affect the reset?

Hello Yang, 

The reset signal does not have a falling edge requirement since it is level triggered. Also I believe that SPI communication should not interfere the reset, By looking at the schematic, all of the connections and signals look right. The key point is that the device resets normally if the pin is shorted to the ground. It makes me believe that the issue is coming from the reset signal that is supplied elsewhere. Apart from that I do not see any other apparent issues that can cause such behavior. Let me follow up with my design team and see if they could help with this issue.

Thank you,

Illia Volkov  

Thank you for your active answer to this question, I will continue to pay attention to it, 
please let me know if there is any progress.

Illia will get another action for you tomorrow.

Thanks,

Paul

Hello Yang, 

A few other things that could potentially be helpful:

Just to make sure, when you are measuring the reset signal, you are connecting the ground probe of oscilloscope to the ground terminal of the DAC, correct? If not, please try to connect said probe to the ground of the DAC and measure the reset signal that way to confirm that DAC indeed sees it as "LOW". 

Another suggestion is to make sure that all of the digital lines are powered by the digital signal. I see the pull up to reset control line is powered by analog signal, try connecting it to the digital power supply instead. That could also potentially affect the behavior that way. 

One of the things that I think might be causing such behavior is the fact that optocoupler might be sinking current while it is in the off state. Could you please measure current at the  nRST pin while the line is off to see how much current is being sank. If the value is high, that could potentially cause the issue. Maybe even try to swap the optocoupler, and see if that potentially solves the issue.  

Also, to clarify, what is the value of your pull up resistor to nRST line? If it is not, could you try replacing that resistor by a resistor between 3.3k and 10k Ohms, and see if that helps? 

Please let me know if any of these actions helped.

Thank you, 

Illia Volkov 

yes, I am connecting the ground probe of oscilloscope to the ground terminal of the DAC. I replace that resistor by a resistor  10k Ohms, It don't helps.If all of the digital lines are powered by the digital signal, Does isolation still make sense? Because of the application scenario of the device, isolation must be required. If I can remove the optocoupler, the reset can be completed normally. So the problem can be locked due to the isolation of the optocoupler. So do you have any good suggestions to complete the reset function and the isolation requirements?

Hello Yang, 

Try to measure current at the reset pin when the signal goes low. One of the thoughts I had is during off state of optocoupler it might be sinking too much current from the device hence not letting it to reset properly. Let me know what the value is.

Thank you,

Illia Volkov 

I am letting the customer test it. Excuse me, how many amps can meet the requirements?

Would you tell me how many amps can meet the requirements? Thanks!!!

Hello Yang, 

What is the reading? I am not entirely sure on the exact requirements, but I will check with our design team. 

Thank you, 

Illia Volkov