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ADC34J24: LMFC COUNT INIT

Part Number: ADC34J24

Hi Experts,


Good Day


I hope you're doing fine.
I need your help. One of our customers is asking below setting.


Question 1) If K=8 in the FRAMES PER MULT IFRAME field of register 31, does the LMFC count range from 0 to 8, and when it reaches 8, does it become 0? Or is LMFC always 0-31?
Question 2) When the LMFC count ranges from 0 to 8. Listed in register 3C. There is a description "the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31.", but if the LMFC count does not reach 31, will K28.5 continue to output?

Thank you


Regards,


Josel Go

  • Hi Josel,

    The K value just represents the number of frames in a single multi-frame window. This is periodic, so you can think of it as counting from 0 through 7 if you'd like before the start of the next multi-frame.

    During CGS (code group synchronization), the FPGA pulls SYNC low to start CGS. The ADC then starts to transmit K28.5 characters (after the LMFC COUNT reaches 31) and when the FPGA receives four consecutive K28.5 characters, the FPGA pulls SYNC high and the ADC starts to transmit the ILAS (initial lane alignment sequence). During the ILAS is when each of the lanes are aligned to each other (on the rising edge of the LMFC).

    The LMFC COUNT INIT in register 0x3C is referring only to the number that the LMFC starts at. The counter still has to reach 31 for the K28.5 characters to begin. The image below is from a TI blog post called "How to bring up your link" and contains information and graphics related to the JESD link bring up.

    Regards, Chase

  • Hi Chase,

    Good Day

    Thank you for this valuable response.

    This is just for clarification.
    Is this mean that any value of K. LMFC will still count from 0 to 31?


    Regards,


    Josel Go

  • Hi Josel,

    Yes, your understanding is correct.

    Regards, Chase