Hello,
My application will use the ADC12DJ3200QML in JMODE0 (single-channel) and subclass 0 (single device, no SYSREF synchronization).
According to ADC datasheet, the JESD204B synchronization is initiated by the FPGA (data receiver) through the assertion of the SYNCSE (or TMSTP+/-) signal with the setup/hold requirements with respect to multi-frame boundary (figure 6-1).
In my subclass 0 application, there is no SYSREF clock allowing my receiver receiver FPGA to know the multi-frame boundary.
I suppose I have to determine the multi-frame boundary through my JESD204B FPGA core and thereby meet the SYNC setup/hold requirements correct ?
Should I instead initiate the JESD204B synchronization through the SPI bus ? It would be simpler.
Thanks
