Hello,
I am using an Arria 10 FPGA, SERDES IP to receive data from the ADC3444. I am not using the bitclk, only frame clock through a PLL for both bit latching and frame separation.
While the datasheet specifies timing of databits vs. bitclk it does not explicitly state the timing of the frame clock vs. data bits. Can I extrapolate the frame clk timing from the bitclk timing?
