DDC112: How to acquire time stability

Hi Takemura san,

Thanks for the detailed descriptions.

May I ask some questions for clarification and gather more info?

0. Does HAMAMATSU suggest use a pure integrator circuit for this photodiode? Or, do they suggest use Hybrid Integrator with TIA? DDC112 is a purely integrator device.

1. could you please clarify what does it mean by "time stability"? Does it refer to measured noises or signal variation overtime(e.g. 1 hr)?

2. Does customer happen to have/use a DDC112 evaluation kit/board(EVM)?

3. "My customer attached a resistor of 1Mohm or 330kOhm to AIN pin instead of PHOTODIODE (S6429-01 made by HPK) in order to see the time stability (1 hour) of the ADC DDC112Y. However, the measurement result in that situation has much more noise than when PHOTODIODE is attached, and they can't not evaluate the stability of ADC."

Comments: Photodiode itself is already a sensitive device that could generate some noises due to its stimulus and the related variation. If the purpose/goal is to understand the ADC's performance and intrinsic noises first, it's suggested to isolate/eliminate any outside/external sources(e.g. photodiode(s)) that might add noises.

E.g. Without using/connecting any external signal source(e.g. Photodiode), customer could short input to GND directly or via a pull down resistor to GND. Again, Customer's GND also needs to be clean in their settings/environment.

Also, Have customer tried the datasheet page 12~13 and EVM user guide page 21 "Test Mode"?

4. Also, we don't know if customer is doing the test with our EVM board, or their own customer board?
If they are using their customer board, please make sure customer's boards follow the guideline in datasheet page 25 Section LAYOUT, and all other power supply and reference voltage requirement listed in page 3 REFERENCE and POWER-SUPPLY REQUIREMENTS. And Page 11 Voltage Reference and/or FIGURE 6.

And, does customer add any external capacitors to CAPxA, CAPxB pins? That could also affect the noises and stability.

5. What does it mean by "1048575 of FFFF"? And, I do not see the related info in data sheet P23? Please clarify/specify whenever a number/value is mentioned, Is such number/value referred to ADC code(count) or the input signal unit(voltage, current or charges)?

6. Open circuit doesn't mean it's GND. Open could mean open, floating, unknown, high voltage(depending on the environment), so the reading/measurement could be anything. Only GND is/means GND or a path(e.g. via a pull down resistor) to GND could be GND if and only if the GND is clean.

Thanks.

Hi Eduardo, ChienChung

Thank you for your answers.

I'll share more information with you.  In addition to that, there are some points I want to confirm.

1. could you please clarify what does it mean by "time stability"? Does it refer to measured noises or signal variation overtime(e.g. 1 hr)?

=> The customer is concerned about the drift phenomenon, and "time stability" refers to drift measurements.

They are investigating the cause of the drift, and as part of that investigation they are looking at "time stability" of the ADC (how the ADC changes over time).

However, at present, the measurement of "time stability" is not successful due to large noise.

2. Does customer happen to have/use a DDC112 evaluation kit/board(EVM)?

=> They use their established board and don't have TI's EVM. 

3. "My customer attached a resistor of ...

=>　In their time stability measurements, they use a 1MOhm or 330kOhm resistor without a photodiode.

-----------------------------------

I am assuming that for time stability they want to see how output changes with time for a given fixed input.

=> This is right. 

Range1 is quite sensitive range. Looks like they ...

=> Is it correct to understand that in the time stability test of the ADC, it is better to attach a very large resistance such as 20 MOhm to AIN in order to stabilize the input (make the error due to AIN << the error due to ADC)?

If they ground the input, the small input bias voltage of the input will get divided by "zero" resistor and create a large current that can saturate the device. So, shorting to GND is not a good option.

=> Is it correct to understand that AIN should not be shorted to GND for time stability measurements? Also, is there any problem in shorting unused input pins to GND in normal use? (They're thinking of treating unused pins as such, referring to other E2Es)

Thank you for your help.

Best Regards,

Taito Takemura

Hi,

"They are investigating the cause of the drift, and as part of that investigation they are looking at "time stability" of the ADC (how the ADC changes over time)."

Yes, this is important to figure what might be the source of drift? is it from the sensor/transducer or the physical stimulus themselves e.g. photons or particles?

 "at present, the measurement of "time stability" is not successful due to large noise"

Yes, drift and noises could mean different things and will need to be dealt/tackled differently. And, whether the noises bothers you depends on your signal strength(magnitude).

drift, after understand the root cause, it could be compensated/calibrated by baseline restorer or digitally by equations(hopefully it's linear).

noise, after understand the root causes, sources and the frequencies, it requires different solutions according to the root causes? e.g. is it optical noises, physical/mechanical noises or electrical noises? can people reduce/attenuate/suppress the noises by optical method, physical/mechanical methods, or electrical analog and/or digital methods?   

"They use their established board and don't have TI's EVM. "

Have or could they try the tests with TI's EVM?

Thanks

Hi Edu, ChienChung

Thank you for your comment.

Based on your comment, the customer measured "time stability" again.Could you give me your opinion on this measurement?

- They made sure their board followed the 'Layout', 'REFERENCE and POWER-SUPPLY REQUIREMENTS' and 'Voltage Reference' on the datasheet and found no violations.

- When they measured with ch1 and ch2 input open, there was no noise as much as the previous measurement (ch1 and ch2 input attached to the resistor) and there was no problem.

- At that time, ch1 will always be 0, and ch2 will be around 2000 and will be time-drifted.

 (Q1) Why does it happen that ch1 is "0"?

 (Q2) When and under what conditions does time drift occur? Could you tell me if there are any conditions where drift is likely to occur?

- Measurement results for one hour of ch1 and 2

Thank you for your help

Best Regards,

Taito Takemura

Sorry Taito-san I don't understand, you say that ch1 is "0" but picture shows not zero, isn't it?

In the picture, there is about 500 codes noise peak to peak. That looks like a lot. According to DS, in range 1, we should see about 8 counts rms. If not clean, I can't trust that such a precise measurement is properly done. Do the have the system in a shielded box?

As explained, drift can come from few sources. Temperature changes, change in voltage supply and inherent drift (due to low frequency noise, aka, flicker). From the magnitude of the drift in the image, I would think that is due to temperature or voltage supply changes, not the intrinsic value given on the DS.

It also looks a bit funny that the two are quite symmetrical...

But more strange, even, is the initial offset value. It should be closer to 4096. Depending on the device looks like one can get up to 600 codes of offset, but the plots above seem to show more than that.

BTW, which exact device are they using? 

Regards,

Eduardo

Hi Eduard,

I made a mistake in the attached image, so I will send the correct information again.

(1) Measurement results for 1 hour with both channels 1 and 2 open.

(2) Measurement results when PHOTODIODE (S6429-01 made by HPK) is attached to the same board, and the PD is measured in a light-shielded state for 1 hour.

Best Regards,

Taito Takemura

Hi Takemura-San,

I see only one figure you post right here. Does this figure contain/include both of (1) and (2) measurement results? Or, One figure is missing?

What might be the unit at the Y-axis?  Is it ADC count(code)?

If it's ADC count, then the trivial drift over 1 hour agrees with Eduardo's statement "As explained, drift can come from few sources. Temperature changes, change in voltage supply and inherent drift (due to low frequency noise, aka, flicker). From the magnitude of the drift in the image, I would think that is due to temperature or voltage supply changes, not the intrinsic value given on the DS."

Are you trying to show that with the same configurations and settings, but Ch1 and Ch2 read out different values? I.e. when both Channels are open, Ch1 reads around 0 and Channel 2 read around 2000.

What was the Range and Integration Time used?

And, what was the VREF, AVDD, DVDD and CLK ?

If it's indeed that all the configurations/settings are the same, but Ch1 and Ch2 read very differently. Next step might need to dig into customer's digital communication Timing diagram according to datasheet Figure 12, 14 and 15, or more.

Thanks

Here is the image of (2)

Hi ChienChung

Thanks for your quick comment. I'll complement the information.

I see only one figure you post right here

=> Sorry. I missed to paste the other picture. I attached the image of (2) again, so please check it.

What might be the unit at the Y-axis?  Is it ADC count(code)?

=> Yes, it's correct.

Best Regards,

Taito Takemrua

Hi,

Thanks for the plots.

Are both photo diodes the same one and connect in the same polarity or bias voltage?

And, again, just to clarify -

Are you trying to show that with the same configurations and settings, but Ch1 and Ch2 read out different values? I.e. when both Channels are open, Ch1 reads around or solid 0 while Channel 2 reads around 2000?

If it's indeed that all the configurations/settings are the same, but Ch1 and Ch2 read very differently. Next step might need to dig into customer's digital communication Timing diagram according to datasheet Figure 12, 14 and 15, or more, and how they decode the Channel 1 data?

Also, I read the following -

"

Does customer happen to have/use a DDC112 evaluation kit/board(EVM)?

=> They use their established board and don't have TI's EVM. 

"

Could we suggest them buy/use an EVM?

Thanks

To add... Please also comment if their setup is within a shielded box as their peak to peak noise looks too big.

Thank you,

Eduardo

Hi ChienChun,

Thank you for your comment. I followed up on the customer's progress to see what's going on. Unfortunately it seems the problem is still there.

I'll share the information with you. Could you please give me your opinion on the following matters?

(1) When they raise the input pin leg of DCC112Y and take the data away from the pattern, the ADC drift will disappear. At the time the ADC values of IN1 and IN2 are around 4000, but the values differ by 100 to 300. The data sheet says that it will be 4096 when there is no input, but is there a difference between 100 and 300 values? 

(2) DCC112Y can be measured in pA units. In accordance with the DCC112Y data sheet instructions, IN1 and IN2 are guarded with GND on the board pattern. Will there be a leak current between IN1/IN2 and GND? Could that leakage current be the cause of the drift? If it is so, how many millimeters should be separated between IN1/IN22 and GND?

Best Regards,

Taito Takemura

Hi Takemura san,

(1) May I ask what does " When they raise the input pin leg of DCC112Y and take the data away from the pattern" mean? What does it mean by "raise" and what does it mean by "take data away from the pattern"?

Input floating basically means zero input current except for input parasitics. So it should give a result around 4096 (without taking into account offset errors)

Regarding to (2), Please take a look of the layout guideline in datasheet page 25,26 -

Power Supplies and Grounding

and

Shielding Analog Signal Paths

and, customers may take a look of the PCBA gerber files for DDC112EVM for layout reference -

https://www.ti.com/product/DDC112#design-development

and encourage to take a look of the DDC112EVM schematic design in evm user guide page 24 ~41

https://www.ti.com/lit/ug/slau234a/slau234a.pdf?ts=1664375494529&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FDDC11XEVM-PDK

Again, does customer have an DCC112 evaluation kit/board(EVM)? If not, it's challenge to guide and/or troubleshooting.

Thanks.

Just to add,

Offset error is in Range 5 (250pC) specs as ±200 ppm of FSR (basically codes) and ±600 ppm of FSR max for the UK/YK version. For a more sensitive range it is likely higher. So, 100 or 300 difference seems within spec./reasonable.

IN1/IN2 are theoretically at the same potential as the GND, so, no current flow between those. That's is fundamentally the reason a guard is designed like this. IN1 and IN2 are not exactly GND (see DC Bias Voltage, input VOS spec on DS). More like fractions of mV, so, I don't think that is the reason for leakage, even if the IN1/IN2 were extremely close to GND.

I recommend to setup a call with customer to get this solved once and for all...

Regards,
Edu