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ADC12DJ3200EVM: AD12DJ3200 GUI subclass1

Thakur Rohit Singh
Prodigy 110 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200, LMK04828

Hi team

What settings to be enabled in ADC12DJ3200 GUI  for JESD204B subclass1 ? How to set for SYSREF clock?-

-trs

  • 0
    TI__Mastermind 20541 points

    Hi Rohit,

    To enable subclass1 you will need to apply the SYSREF signal to the ADC. and also do following register writes to enable the sysref receiver and sysref processing

    Addr          value

    0x0029    0x70 // Enable sysref reciever, processing and zoom

    0x02B0    0x01 // Auto Sysref cal.

    Here is sysref frequency calculationn

    Dev_clk is clock frequency applied to the ADC. R factor, K an F are given the datasheet table 18 for each mode. 

    Serdes Rate = Dev_clock x R factor 

    Sysref freq = Serdes Rate/(K x F x 10 x n) where n is positive integer. n = 1,2,3,4.......

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 110 points

    Hi 

    Thanks very much!

    I wrote the register 0x029 and 0x2B0 with 70 and 01 respectively . I have follow up questions.

    1) After programming the ADC when i read register 0x208, it gives value 7C. I believe this is expected. Is there anything else we need to set for SYSREF in the ADC12DJ3200 GUI?

    2) SYSREF which is generated from LMK04828 on the ADC12DJ3200 EVM, when captured at the the receiver (FPGA side) seems to be continuous signal instead of one pulse. Is this expected from ADC12DJ3200 EVM interface?

    3) Do I need to check its alignment w.r.t to LMFC period or frame clock to make sure deterministic latency is achieved?

    Thank you in advance 

    -trs

  • +1 in reply to Thakur Rohit Singh
    TI__Mastermind 20541 points

    Hi trs,

    1. Yes 0x7C is expected value. 

    2. Yes continuous syserf is required by the ADC to do the auto sysref calibration. One pulse is only used when sysref is DC coupled to ADC which is not the case with the ADC EVM. 

    3. You will need to make sure SYSREF freqeuncy is equal to or integer divide for LMFC clock frequency.

    Regards,

    Neeraj