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ADS5294: ADS5294 SYNC pulse timing

Part Number: ADS5294

Hi,

We are using single device ADS5294,  no decimation. Our sampling frequency is 10Mhz, 2-wire mode.

We want to  output a single pattern.

We did the experiment with external sync: Steps we followed:

    1. Soft RST( configure registers after RST)

     2. EN_SYNC in ADC

     3. TP_HARD_SYNC Enabled along with the test patterns

   4. send a hard sync pulse 

    5. Write single custom pattern

   6. enable SINGLE_CUSTOM_PAT

what is the correct way to go back from test mode to acquiring real samples

Just turn off/disable  SINGLE_CUSTOM_PAT only or  disable 2 and 3 as well above?

  

LT

  

   

     

   

  • Hi LT,

    Thanks for sharing your query.

    Let me get back to you by tomorrow on this.

    Thanks & regards,

    Abhishek

  • Hi LT,

    Just curious to know why do you want to use the SYNC feature for an single device? Also SYNC can be applied to synchronize the ramp pattern on various output channels but if you are putting a constant pattern (custom pattern), then there you a have a constant pattern and the device will keep giving the same data so synchronization is not required there.

    So if you want to synchronize with a test pattern - then the right order should be 

    1. Soft RST( configure registers after RST)

    2. EN_SYNC in ADC

    3. TP_HARD_SYNC Enabled along with the test patterns

     4. Enable the test pattern

     5. Send a hard sync pulse on the device pin

      

    Then if you want to go back to normal operation mode2, you dont have to disable 2 and 3, just disable the test pattern.

    Thanks & regards,

    Abhishek

  • Hi Abhishek,

    I don't think i need to use the sync feature on a single device, but the question came up a lot in the forums. 

    I agree for a single pattern you dont need a synq.

    Do you need a synq when you go to mode2 when start acquiring channels is the ultimate question?

    LT

  • Hi Lach,

    The reason for usage of SYNC is to match the latency of the data from multiple channels/device. For example, you synchronize the data with sync at the AFE side, then you capture the data at the FPGA side and got the ramp correctly at all the channels. It means that the latency is matched between the device and the FPGA. It is more of a debug signal.

    However if you are sure of the latency at the FPGA side. then this SYNC is not required you can capture the data directly.

    I hope it answers your question.

    Thanks & regards,

    Abhishek