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TI-JESD204-IP: RX_LN_DATA_WIDTH Parameter for 4 Lane Operation of ADS54J69

Sajid Ali
Prodigy 20 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADS54J69

The TI-JESD204-IP documentation specifies that the RX_LN_DATA_WIDTH parameter has only the following valid options: 32, 64, and 128 bits.

However, I want to run the ADS54J69 using 4 lanes at 4.9152 Gbps which according to its data sheet (see figure 74 on page 36) has a lane data width of 16-bits. 

Is there a way to configure the TI-JESD204-IP to support this mode or do I need to use another JESD204 IP (possibly from Xilinx)?

Thanks.

  • +1
    TI__Mastermind 23780 points

    Hi Sajid,

    The RX_LANE_DATA_WIDTH will affect the number of samples (in this case, 16-bit samples) which need to be unpacked from each lane's decoded data each fpga clock period. The RX_LANE_DATA_WIDTH is set to 64 by default for the TI 204c IP (And I believe Xilinx's IP has a fixed lane data bus width of 128 bits).

    This is still compatible with 16 bit devices. All that is needed is to unpack the data into consecutive samples based upon the ADS54J69's frame assembly format. Remember that because RX_LANE_DATA is a 64-bit bus, this will actually contain 16 samples resulting from 4 of the 16-bit samples on each lane occurring within the 64 bit data window, and across 4 lanes. Each of the ADC channels will have 8 samples on the rx_lane_data bus each fpga clock period.

    Regards, Chase