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ADS42JB69: Variability in the phases between channels

Part Number: ADS42JB69

Hi Guys

Customer asked:

 We having been using these ADCs for a while now. We are successfully receiving samples across the JESD204B links. Furthermore, we have been able to successfully synchronise up to six of these ADCs in a system using a fanout clock tree from a single master clock source. This appears to all be working properly. However, we have recently picked up an issue and would like some advice on it please.

 

The problem description is as follows:

We sample our ADCs at fs. We use the 10MHz from our master clock source to drive the reference 10MHz input of a signal generator. We use a splitter to feed an identical single tone input to all the channels in our system. We then measure the relative phase differences between channels and plot how this phase difference varies over time.

 

When we input a signal at fs/4 or 3fs/4, we get very good phase consistency (from sample to sample) between channels of the system. However, as soon as we move slightly off this frequency by, say 1 to 10kHz, we see a large variability in the phases between channels of up to 3 degrees. As we move our input signal further away from fs/4 or 3fs/4, the situation improves. At a roughly 50kHz offset we achieve a 0.2 degree phase variation between channels which is sufficient to meet our requirements. It should also be noted that the situation is worse at 3fs/4 than at fs/4.

 

Our one thought is that this could possibly be related to the dither feature of the ADS42JB69. Would it make sense for dither to introduce this large phase variability at close to fs/4 or 3fs/4? Is it possible to disable the dither feature? We couldn't find any options in the device register map.

 

We know that the ADS42JB69 is a pipelined ADC and so are not expecting any form of interleaving spurs. Do you have any idea what could be causing this large phase variability at close to fs/4 or 3fs/4? We believe that the 'synchronous sampling' affect of having the signal generator locked to the same clock source as the ADCs explains why things get considerably better at exactly fs/4 or 3fs/4. But we are scratching our heads as to why we are seeing such large phase variation at a small offset from this frequency. Unfortunately the current system is not performing well enough to meet our requirements and any advice would be greatly appreciated.

Thanks

Rodney