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TSW1400EVM: Modifying FPGA bitstream to optimize the time it takes for the firmware to store subsequent data

Part Number: TSW1400EVM

Hi.

This is related to my previous question on TSW1400 repetitive capture process. I wanted to capture a desired number of samples (say 8096 samples) every 0.5ms upon reception of a trigger to the TSW1400(Trigger rate = 2000Hz). I am currently using ADS54T02EVM. Previously I was informed that it would take atleast 100-300ms for the data to be stored and subsequent block of sample to start capturing. So, in this regard, I wanted to know if the FPGA could be re-configured with any custom bitstream thus bypassing the delays in capture due to the current firmware configurations to achieve the desired capture rate. 

Warm Thanks & Regards,
Adithya N