TSW14J57EVM: TSW14J57EVM

gaurav malhotra

Part Number: TSW14J57EVM

Hi,

We are interested in TSW14J57 & ADCxxDJxx00RF-TRF1208 Evaluation Module to build a prototype , need to know the capabilities of the FPGA on the EVM, specifically if we can write our own RTL into it and how much (code space) does it have and if there are any limitations on the clock speed of the logic.

If we can connect with an application engineer, that would really help.

thanks!

over 2 years ago

0 Rob Reeder over 2 years ago

TI__Mastermind 37740 points

Hi Gaurav,

I believe the answer is no, but I will confirm, that we don't allow you to use or reconfigure the RTL code in the FPGA of the TSW data capture board.

I think it would be best to use a Xilinx devkit or similar to accomplish this. The ADCxxDJxx00RF-TRF1208 Evaluation Module will connect to these types of dev kits that have an FMC connector.

Regards,

Rob

0 Rob Reeder over 2 years ago in reply to Rob Reeder

TI__Mastermind 37740 points

Hi Gaurav,

I should also point out that the J47 has an Intel FPGA.

I might be better to request a few examples from our JESD IP link: www.ti.com/.../TI-JESD204-IP

Here we can get you jump started on interface development.

Regards,

Rob

0 gaurav malhotra over 2 years ago in reply to Rob Reeder

Prodigy 180 points

Hello Rob, Thanks for the reply. Please do check if we can write into the FPGA of TSW data capture board. It'll be better for us to go with an all TI solution. If TI can provide a custom solution whereby we can write into the FPGA, we can also consider that.

Let us know.

thanks

Gaurav

0 Rob Reeder over 2 years ago in reply to gaurav malhotra

TI__Mastermind 37740 points

HI Gaurav,

Unfortunately, no you cannot write into the FPGA of the TSW data capture board.

It might be better to request a few examples from our JESD IP link: www.ti.com/.../TI-JESD204-IP

Please consider this route instead and we can help your development that way.

Regards,

Rob

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TSW14J57EVM: TSW14J57EVM