ADS131M06: ADC not applying configuration

Stanislav Husar

Part Number: ADS131M06

Hello,

I have problems with ADS131M06. On MCU boot, I am resetting it via SYNC/RESET, then sending WREG to clock register. Here I want these settings:

External clock source 8.192MHz
External reference voltage
All channels
250SPS

After this sequence, I apply 250Hz signal to SYNC/RESET, and poll DRDY. On falling edge, I am sending NULL command, and reading samples.

Based on this screenshot, I believe that I am complying with SPI timing requirements. Can you see some mistake?

Here is init sequence:

Whatever I am trying to put to clock register, here is what I get on DRDY:

ADC is definitely not operating at 250SPS. Seems to me, that it is operating at 4kSPS, but it does not have enough time to transfer all ADC data in time.

Here are some examples of ADC data transmission:

I do not even know, whether these are actual ADC data, or some mess. I have tied inverting inputs to reference voltage. Right now noninverting inputs are floating, they will be connected to single-ended signal from instrumentation amplifier.

Can someone see what am I doing wrong?

Thanks in advance,

Stanislav

over 2 years ago

0 Cole Macias over 2 years ago

TI__Mastermind 18900 points

Hi Stanislav,

Can you stop toggling the SYNC/RESET and Read the Device ID (reg: 0x00)? If you cannot successfully read the default, then we'll narrow down to what the issue might be.

In general, I don't see any issue with timing or formatting. I noticed that a MISO word, as a result of the NULL command, results in an impossible STATUS response. Before looking at the ADC output codes, I look at the STATUS output (the first SPI word before the channel data) and cross reference that with the default values. Becuase I saw an impossible value, I assume there will be an issue.

For your info, floating inputs can be anything but they usually settle somewhere closer to GND which would result in an output code within the offset voltage specification if you did the conversion from code to voltage. The ADC is always converting, and you can easily probe DRDY to see if its toggling to determine if the ADC is operating at the right data rate.

Once you've confirmed an issue, I will recommend using an oscilloscope, not a logic analyzer, and probe the MISO, SCLK, MOSI, and DRDY signals. Usually, I can find out what's happening there. If you can correctly get SPI commands, change the data-rate and see if DRDY changes in frequency and we can go from there.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

I wrote an independent firmware, where I just read entire register space. Master clock is 8.192MHz, unfortunately I cannot have it synchronized to serial clock. First I have tried serial clock 1.024MHz. Results are in file dump.txt . Then I have lowered serial clock to 8.192kHz. While such a slow clock is definitely unacceptable, I got different results, these are in dumpslow.txt .

I will probe bus on scope ASAP.

Stanislav

dump.txt

Device 0 chip select 0
a0 3f 0 -> ff 26 0
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 7f 93
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 7f
0 0 0 -> 93 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 7 f9
0 0 0 -> 30 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 3 fc
0 0 0 -> 98 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 1 fe
0 0 0 -> 4c 0 0
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> ff 26 0
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 ff
0 0 0 -> 26 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 7f
0 0 0 -> 93 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 ff 26
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 3 fc 98
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 7f 93 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 1f
0 0 0 -> e4 c0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 1f
0 0 0 -> e4 c0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 7f 93
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
Device 1 chip select 1
Device 0 chip select 0
a0 3f 0 -> ff 26 0
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 7f
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 3f
0 0 0 -> c9 80 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 1f
0 0 0 -> e4 c0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 1 fe
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> ff 26 0
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 ff 26
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 ff 26
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 ff 26
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 3 fc 98
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 1f e4 c0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 1
0 0 0 -> fe 4c 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 1
0 0 0 -> fe 4c 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
Device 1 chip select 1
Device 0 chip select 0
a0 3f 0 -> ff 26 0
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 ff
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 7
0 0 0 -> f9 30 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 ff
0 0 0 -> 26 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 ff
0 0 0 -> 26 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 7f
0 0 0 -> 93 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 1f e4
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> ff 26 0
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 1f
0 0 0 -> e4 c0 0
0 0 0 -> ff f f2
0 0 0 -> 60 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 7f 93 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 3f
0 0 0 -> c9 80 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 ff
0 0 0 -> 26 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 20 ff
0 0 0 -> 26 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 ff 26
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> 0 0 0
0 0 0 -> ff 26 0
0 0 0 -> ff 26 0
Device 1 chip select 1

dumpslow.txt

Device 0 chip select 0
a0 3f 0 -> 55 aa 55
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> 55 aa 55
0 0 0 -> 7f bf 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f ff
0 0 0 -> 55 aa 55
0 0 0 -> fe ff fe
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe fd
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 5f
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 55 aa 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 5f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> 5f af 57
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 5f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
Device 1 chip select 1
Device 0 chip select 0
a0 3f 0 -> bf 5f af
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> af 5f af
0 0 0 -> 55 aa 55
0 0 0 -> 7f ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fa fd
0 0 0 -> 55 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> ff ff ff
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> ea d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
Device 1 chip select 1
Device 0 chip select 0
a0 3f 0 -> f5 fa fd
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> fd fe fd
0 0 0 -> 55 aa 55
0 0 0 -> ea d5 ea
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 55 aa 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 5f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa f5 fa
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa 55
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 55 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> ab 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe fd fe
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> ff fe ff
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 5f
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 5f
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fe ff fe
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
Device 1 chip select 1
Device 0 chip select 0
a0 3f 0 -> 55 aa 55
Device 0 chip select 1
Device 0 chip select 0
0 0 0 -> 55 aa 55
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> ea f5 fa
0 0 0 -> af 57 ab
0 0 0 -> 55 aa 55
0 0 0 -> 7f ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> bf 5f af
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff 7f
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 5f af 57
0 0 0 -> aa 55 aa
0 0 0 -> ff ff ff
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> ab 55 aa
0 0 0 -> 55 aa d5
0 0 0 -> 7f bf 5f
0 0 0 -> aa 55 aa
0 0 0 -> fd fe ff
0 0 0 -> 55 aa 55
0 0 0 -> aa d5 ea
0 0 0 -> af 57 af
0 0 0 -> 55 aa 55
0 0 0 -> ff ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
Device 0 chip select 1
Device 1 chip select 0
a0 3f 0 -> fa fd fe
Device 1 chip select 1
Device 1 chip select 0
0 0 0 -> fa fd fe
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> d5 ea f5
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> ff 7f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
0 0 0 -> f5 fa fd
0 0 0 -> 57 ab 55
0 0 0 -> aa 55 aa
0 0 0 -> bf 5f bf
0 0 0 -> 55 aa 55
0 0 0 -> fe ff ff
0 0 0 -> aa 55 aa
Device 1 chip select 1

0 Stanislav Husar over 2 years ago in reply to Stanislav Husar

Prodigy 40 points

Okay, so I have checked SPI signals on scope, it looks okay. Given that I have used high-performance scope, and generic cable from scope probe to pcb, noise level is acceptable.

MCLK is asynchronous to SPI clock, but SPI is 8x slower than MCLK. So I believe that ADC has enough time to correctly rx/tx data.

Stanislav

0 Stanislav Husar over 2 years ago in reply to Stanislav Husar

Prodigy 40 points

I have tried multiple different frequencies for SCLK. Changing bus speed does change what mess I am getting, but I never found its meaning. I have tried adding 0x000000 words after RREG command, to check if I am not using short frames in wrong way. Nothing helps.

I have also tried another PCB, but I get the same behavior. So unless I got a faulty batch, what I am getting is some property of ADS131M06, not failure of single device.

Stanislav

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

Stanislav Husar said:
Okay, so I have checked SPI signals on scope, it looks okay. Given that I have used high-performance scope, and generic cable from scope probe to pcb, noise level is acceptable.

Agreed, the overshoot is not too bad, looks like ground connection is solid. Looks like it's leading to FW.

Stanislav Husar said:
I wrote an independent firmware, where I just read entire register space.

An interesting experiment, but its clear we can't trust what the MCU gives back. The logic analyzer and oscilloscope data is what I'll primarily be looking at.

Cole Macias said:
I will recommend using an oscilloscope

On the topic of your first oscilloscope screenshot where you try to read the first register, it looks like you missed a very important note in the datasheet. Essentially, MOSI latches on falling edge of SCLK and its clear the bits transition on the falling edge. Here's the text in the datasheet:

Try to fix that and see if we can get some the default value in the datasheet. It does not matter if the SCLK and MCLK is synchronous. It helps with performance and jitter but its clear we can't even communicate with the device correctly. We'll need to solve that first.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

Thanks for your reply. I will look tomorrow at behavior in different SPI modes, hopefully I will get valid data.

As for serial clock. I am glad that it works with asynchronous SCLK/MCLK. I would prefer synchronous clock, but with my MCU selection, this isn't possible.
Then, what is truly maximum SCLK? Is this related to MCLK, or can it be 25MHz regardless of MCLK? I would prefer fastest clock, that gives reliable transmission.

Stanislav

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

Maximum SCLK is 25MHz as you said, no dependence on MCLK. If there is a dependence, the specification will be given as an equation in the typical/max/min columns or the unit will be related to a different spec, t_MCLK for example. You can see it in the t_w(RSL) specification as an example.

I look forward to your reply tomorrow.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

I am completely lost now. I tried virtually all possible SPI configurations, nothing works for me. Even modes 2 and 3, slow SCLK, faster SCLK than MCLK, MSB first, LSB first,...everything I can think of.

I would like to ask community to record on logic analyzer proper sequence to read register space. Or draw it, if you know for sure what should be there.

Stanislav

0 Stanislav Husar over 2 years ago in reply to Stanislav Husar

Prodigy 40 points

Here is part of my schematic, are all connections correct? MCLK is 8.192MHz crystal oscillator, AREF is 1.25V voltage reference, VCC and +3V3 are connected to LDO voltage regulators (there are also some electrolytic caps).

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

In general, the connections look fine. If you power up the device and see DRDY toggling at the default sampling rate (or half of it) then you have successfully powered up the device. Directly connecting the reference voltage to the negative inputs isn't recommended because the increasing current draw from the reference might introduce noise. Most people use a voltage divider from AVDD if they want to use puesdo-differential inputs.

But none of this matters for SPI, you can even disconnect MCLK and still be able to communicate with the device. I will stress again if you have SYNC toggling during any of this, you will run into issues. In your first screenshot that DRDY wasn't periodic which is usually from SYNC resetting the filters.

I also noticed that your MISO and MOSI were tied together at one point in the previous logic analyzer shots, I would definitely look into if you're still having the issue and why that is the case.

Stanislav Husar said:
I am completely lost now. I tried virtually all possible SPI configurations, nothing works for me. Even modes 2 and 3, slow SCLK, faster SCLK than MCLK, MSB first, LSB first,...everything I can think of.

You can do it! I wouldn't recommend trying different things and seeing if they work, look at the data with an oscilloscope, what does it say? Can you prove that your timing is correct? I'd also only work on one ADC at a time, just to make things simpler.

In general SCLK speed doesn't matter as long as you are below 25MHz, faster or slower influences nothing as your code shouldn't be adding delays that scale on the SCLK frequency.

Though I've already mentioned most of what you should be doing, I find this to be a concise blog about what we are doing:

[Blog] Help! I can’t talk to my data converter! What’s wrong?

Stanislav Husar said:
I would like to ask community to record on logic analyzer proper sequence to read register space. Or draw it, if you know for sure what should be there.

I'm sure you've seen this but I think its time you look at the oscilloscope and use the time cursors to prove that your timing is correct when you're looking at the read.

I'll see if I can find a screenshot of the protocol. Feel free to post some oscilloscope and logic analyzer waveforms and I will help where I can.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

Thanks for your reply. Yes, I have seen timing requirements. I can compare it to scope, maybe I will find some violation.

Can you also post me correct byte sequence on higher level? Here is what I was trying last time:

Chip select low
Send 0xA1, 0x00, 0x00 (RREG 0)
Here I have tried sending another frame 0x000000
Pulse chip select
Read 5 bytes (send 0x00 while reading)
Chip select high

Is this correct sequence for reading ID register? What would be correct byte-level sequence for writing to CLOCK register, and for reading ADC data?

Stanislav

0 Stanislav Husar over 2 years ago in reply to Stanislav Husar

Prodigy 40 points

Hello Cole,

I have checked timing requirements, at 128kHz SCLK, I exceed minimums by far.

This is how it looks when I send some single-byte value. Data are latched at SCLK rising edge, they are valid on SCLK falling edge.

Here is what I get if I try to readout register space. First six columns are during transmission of A0 3F 00 00 00 00, | denotes chip select pulse, for the rest of transmission I am sending 0x00. After each line I reset ADC. = line denotes swapping for another PCB. Apparently both behave the same, I don't believe both could be damaged.

ff 26 00 e1 22 d5 |e1 3f fa e7 2d 98 e5 bf e3 e5 b6 ed ff de 68 6c 09 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 1f ef |e1 3f b4 e7 2d a9 e5 bf e6 e5 b6 6b ff df ec 7b ad 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 23 5e |e1 3f b5 e7 2d cf e5 bf 64 e5 b6 e7 ff de 92 86 ba 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 b7 |e1 3f 44 e7 2d df e5 bf a4 e5 b6 eb ff de af 08 79 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
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ff 26 00 e1 23 bf |e1 3f 85 e7 2d 3c e5 bf aa e5 b6 ff ff df 5e fc 97 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 23 fe |e1 3f 36 e7 2d 28 e5 bf 80 e5 b6 e1 ff df 47 96 eb 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 1f cf |e1 3f 62 e7 2d 8e e5 bf 19 e5 b6 6f ff de 95 b5 0d 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
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ff 26 00 e1 21 fb |e1 3f f4 e7 2d 8d e5 bf 79 e5 b5 e0 ff de 66 ab 3f 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 cf |e1 3f 00 e7 2d e6 e5 bf 44 e5 b6 ab ff de 84 42 fb 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 23 ff |e1 3f b7 e7 2d 0e e5 bf 9f e5 b7 31 ff df 17 e1 59 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 20 7f |e1 3f 82 e7 2d af e5 bf fb e5 b6 53 ff de 04 1b 72 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 20 ea |e1 3f c0 e7 2d 75 e5 bf 7f e5 b6 98 ff de 4e 30 4f 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 20 a7 |e1 3f 58 e7 2b f8 e5 bf 1f e5 b6 0d ff df fa 5f b7 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 21 a9 |e1 3f 37 e7 2d cf e5 bf 57 e5 b7 40 ff de 5a f0 10 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 ff |e1 3f 96 e7 2d c8 e5 bf a0 e5 b7 55 ff de 4e dd 3a 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 20 ad |e1 3f 5b e7 2d 40 e5 bf 38 e5 b6 cc ff de 07 34 99 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 fb |e1 3f 12 e7 2d a9 e5 bf 84 e5 b6 ba ff de e9 f1 fb 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 fd |e1 3f 9d e7 2d a2 e5 bf c6 e5 b6 ff ff de 9f 12 75 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 23 73 |e1 3f 11 e7 2d a7 e5 bf 79 e5 b6 51 ff de 71 51 a4 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 f5 |e1 3f 25 e7 2d 85 e5 bf 6a e5 b6 4c ff de 85 d3 46 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 b7 |e1 3f fb e7 2d e8 e5 bf f3 e5 b7 0e ff de ae 51 8f 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 20 95 |e1 3f a0 e7 2d 89 e5 bf 25 e5 b6 73 ff de 36 53 af 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 23 ff |e1 3f 58 e7 2d d5 e5 bf cd e5 b7 39 ff de a6 0e 18 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 1f 76 |e1 3f 91 e7 2d c2 e5 bf 10 e5 b7 5e ff de 70 97 78 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 1f f8 |e1 3f 36 e7 2d 42 e5 bf 32 e5 b6 ae ff de d4 a1 03 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 1f f7 |e1 3f e3 e7 2d 7e e5 bf ee e5 b6 a0 ff de 84 a2 69 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 ff |e1 3f 33 e7 2d db e5 bf b0 e5 b7 e4 ff de b3 46 84 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 7a |e1 3f c3 e7 2d 6a e5 bf 2f e5 b7 0c ff de fa bc 26 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 23 bf |e1 3f 14 e7 2d 3b e5 bf af e5 b7 0c ff de 55 8b 6e 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 23 97 |e1 3f 5d e7 2d 96 e5 bf 48 e5 b7 56 ff de 41 e9 68 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 1f d5 |e1 3f 63 e7 2b db e5 bf e8 e5 b6 e8 ff df f9 38 71 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 8f 
ff 26 00 e1 22 db |e1 3f dc e7 2d bb e5 bf 63 e5 b7 3d ff de 7c 5b 1a 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
ff 26 00 e1 21 d9 |e1 3f 8e e7 2d 55 e5 bf ab e5 b6 ac ff df ef b8 e3 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 90 
======================================================================================================================================================================================================
ff 26 00 e1 3e 77 |e1 3f 41 e6 d5 5e e5 bf be e5 d4 4c ff ef a5 f4 b8 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e b7 |e1 3f 31 e6 d5 38 e5 bf 33 e5 d4 ea ff ef 84 bf 91 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e ce |e1 3f 18 e6 d5 b6 e5 bf 34 e5 d5 27 ff ee 75 90 9d 00 e0 3f 00 26 01 00 05 3f 00 05 10 00ff 26 00 e1 3e fd |e1 3f cf e6 d5 cf e5 bf a7 e5 d4 7b ff ef b7 23 1c 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3b d3 |e1 3f ae e6 d5 dc e5 bf 2a e5 d3 cb ff ee d2 0c a3 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3b be |e1 3f 51 e6 d5 aa e5 bf 95 e5 d3 28 ff ee 69 0a 6c 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f f9 |e1 3f a6 e6 d7 67 e5 bf 24 e5 d4 db ff ef ae de a2 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e f3 |e1 3f 1c e6 d5 7c e5 bf e1 e5 d4 16 ff ee 92 95 c3 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f f7 |e1 3f d6 e6 d7 3e e5 bf 00 e5 d4 15 ff ee 05 4b 18 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 98 
ff 26 00 e1 3c fe |e1 3f 8c e6 d5 c3 e5 bf c5 e5 d4 21 ff ee 1a 73 ae 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f 2b |e1 3f d2 e6 d7 84 e5 bf 84 e5 d4 9d ff ee 84 22 5c 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f ee |e1 3f 69 e6 d5 8f e5 bf df e5 d4 9e ff ef b1 6c 1e 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f cb |e1 3f 2d e6 d5 e3 e5 bf 6a e5 d4 12 ff ef b8 c0 b9 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f fe |e1 3f f0 e6 d5 ea e5 bf 91 e5 d4 42 ff ef f7 11 80 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f 5e |e1 3f d7 e6 d7 47 e5 bf 5f e5 d4 e2 ff ef f8 f9 dd 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3a f5 |e1 3f be e6 d5 b1 e5 bf d0 e5 d3 96 ff ee c1 32 3c 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e e2 |e1 3f 7b e6 d5 78 e5 bf d9 e5 d4 14 ff ef b3 e9 50 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f bf |e1 3f c8 e6 d5 ed e5 bf b9 e5 d4 bc ff ef ee 43 bc 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f 9d |e1 3f 48 e6 d5 df e5 bf f9 e5 d3 fa ff ef 80 9a d1 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f fe |e1 3f 0c e6 d5 b4 e5 bf fe e5 d4 36 ff ef f1 99 1e 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e ff |e1 3f 92 e6 d5 cc e5 bf f3 e5 d4 d9 ff ef 6f 59 cb 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3d 6f |e1 3f db e6 d7 63 e5 bf 3c e5 d4 ea ff ef e2 9a ec 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f f6 |e1 3f 9d e6 d5 c1 e5 bf 88 e5 d4 77 ff ef db 73 12 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3d 7c |e1 3f da e6 d5 f2 e5 bf ab e5 d4 a4 ff ef dc ba d9 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f ff |e1 3f 67 e6 d7 33 e5 bf de e5 d4 c8 ff ee 1c 0e 0f 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3b a5 |e1 3f 9d e6 d5 39 e5 bf 22 e5 d3 f0 ff ef 2e f3 cf 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 98 
ff 26 00 e1 3d ff |e1 3f 09 e6 d7 2e e5 bf 35 e5 d5 17 ff ee 31 36 f6 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f c7 |e1 3f f8 e6 d7 25 e5 bf df e5 d5 25 ff ee 28 2b f1 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f db |e1 3f 38 e6 d5 d2 e5 bf 80 e5 d4 c4 ff ef ba a1 29 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e ff |e1 3f a5 e6 d7 0a e5 bf ea e5 d4 52 ff ef ee 5d 49 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3e b7 |e1 3f 8a e6 d5 b5 e5 bf b2 e5 d4 8e ff ef 7e 17 9a 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f ff |e1 3f a3 e6 d7 3e e5 bf d2 e5 d4 b3 ff ef f9 1b 99 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f dd |e1 3f dd e6 d7 1f e5 bf 20 e5 d4 c0 ff ef db 7c b6 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f c1 |e1 3f ee e6 d7 04 e5 bf db e5 d4 b1 ff ee 01 d2 63 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3f bf |e1 3f ea e6 d7 05 e5 bf 0e e5 d4 a2 ff ee 39 02 85 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99 
ff 26 00 e1 3b fe |e1 3f 22 e6 d5 56 e5 bf 96 e5 d4 41 ff ef d3 bd a3 00 e0 3f 00 26 01 00 05 3f 00 05 10 00 3f 0e 00 00 00 00 00 00 00 86 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 02 9f 80 70 99

Stanislav

+1 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

I would do a sequence like this:

Chip select low
- Follow t_d(CSSC) spec
Send 0xA0 0x00 0x00 on DIN
- address: 0x0 and only want to read 1 register so 0x0 (0+1 registers to be read)
- And need to fill up LSB with 0x0 so we have 24 bits for first SPI word
Need to read out 6 channels of data
- Send 0x000000 on DIN for a single channel and do it 5 more times
- We're at 24*7 SCLK toggles or bits at this point
- Keep CS low the whole time, no need to toggle if we aren't done with the whole command frame and read process (Figure 8-23 shows this)
Choose to clock out CRC or don't
- If not raise chip select high and follow t_d(CSSC)
- If so, do another 24 bits then raise CS high
Wait for another DRDY toggle
- In our debug case, you can probably just lower CS again after t_w(CSH) and start the new frame
First 24 bits on DOUT will contain the device ID
- If you're looping, you can send 0xA00000 again if you want
- Our goal is 0x26xx

If your data I see a bunch of 0x26 so you may have gotten the right answer but your MCU interpretation is wrong (why do we see 0xFF at the front?). I'm also see pretty consistent columns while leads me to believe you have good channel data. You also have more "data" than I would expect for a frame. Some where between 8-9 SPI 24bit words until CS should be brought high again.

Once you figure out how to align the MSB on the MCU to the actual MSB coming from the ADC, I suggest you send a NULL (or read address:0x1) and we can read the STATUS register and see what's going on.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

I really hope it is something like that. But what do you mean by MSB misalignment or MCU misinterpretation? Anytime I send something to ADC, I read equal amount of data.

I do not have the PCB with me right now, but I will definitely try this ASAP.

Stanislav

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

Stanislav Husar said:
But what do you mean by MSB misalignment or MCU misinterpretation?

I'm not sure yet. Your oscilloscope screenshot should have data on DOUT and it clearly reads 0xFF. I'd rather fix the obvious issues and see if any behavior persists before we spend some time speculating.

Hope it all works out!

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

Still not there.

Chip select low.

a0 00 00 -> 05 3f 00

00 00 00 -> e1 21 7f

00 00 00 -> e1 3f ef

00 00 00 -> e1 ae f7

00 00 00 -> e1 be 85

00 00 00 -> e0 e7 bf

00 00 00 -> 26 01 00

00 00 00 -> e1 21 6f

Chip select high.

Wait for drdy.

Chip select low.

a0 00 00 -> e5 3f fe

00 00 00 -> 27 3f 00

00 00 00 -> e1 20 fd

00 00 00 -> e1 3f df

00 00 00 -> e1 ae ff

00 00 00 -> e1 be 75

00 00 00 -> e0 e7 53

00 00 00 -> 05 3f 00

Chip select high.

Wait for drdy.

Chip select low.

a0 00 00 -> e5 3f d7

00 00 00 -> e1 3b f5

00 00 00 -> e1 2c b7

00 00 00 -> 27 3f 00

00 00 00 -> e1 21 db

00 00 00 -> e1 3f ef

00 00 00 -> e1 af 5b

00 00 00 -> e1 be bd

Chip select high.

Wait for drdy.

I do not have access to that scope I was sending screenshots.

Stanislav

0 Stanislav Husar over 2 years ago in reply to Stanislav Husar

Prodigy 40 points

I have tried another MCU, I get basically the same response. This rules out MCU malfunction. There must be something with communication, or maybe with the ADC itself?

Stanislav

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

Stanislav Husar said:
a0 00 00 -> 05 3f 00

Funnily enough, the first time you attempt to send a read, we get the correct STATUS register response (0x053F)

Which would come from the response of a NULL. So maybe the MCU's interpretation of MISO is good but MOSI is not sending the expected command.

Stanislav Husar said:
00 00 00 -> 26 01 00

Stanislav Husar said:
00 00 00 -> 05 3f 00

This is where things get confusing for me and I think you need to pull the logic analyzer back out. Very clearly you get the right answers but they're appearing on all the wrong spots. You get your eventual response to a read and a NULL but later and seemingly random. The 0x26xx response was from your read command a well. The rest of the data (e.g. 0xE1xxxx) is clearly standard channel data.

The logic analyzer will let us know if there are any delays or missed data from the MCU side because the math isn't working out for how much you're clocking out.

Stanislav Husar said:
This rules out MCU malfunction. There must be something with communication, or maybe with the ADC itself?

Agreed, and with the result above, I think communication seems to be the issue.

Best,

-Cole

0 Stanislav Husar over 2 years ago in reply to Cole Macias

Prodigy 40 points

Hello Cole,

Thanks for your reply. Good news that you see some sense into the data. I will look at it with logic analyzer. Maybe it is a really dumb problem, these are often hard to find.

Also, how can I contact you during forums maintenance?

Stanislav

0 Cole Macias over 2 years ago in reply to Stanislav Husar

TI__Mastermind 18900 points

Hi Stanislav,

Sounds good! Best of luck.

Don't have the best answer for how to contact us the "support request" ticketing system still comes back to us directly after a couple of days delay so its a bit of wash when it comes to timing. I'll try to see if I can do something for you before we go down for maintenance.

Best,

-Cole

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