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synchronization of multiple DACs 5687

donia elotamni
Prodigy 60 points
Other Parts Discussed in Thread: DAC5687, DAC3282, DAC3484

I would like to synchronize multiple TxDACs, and there is no guarantee that the DATACLK output are synchronized.

I was reading the data sheet of this DAC and i have some questions:

- why are we using the dual clok mode with FIFO disable ou the PLL clock mode for multi DACs synchronization?

- how can we obtain the same internal cloking phase in the chips using the same CLK1/CLKC1?

- what are the most important points to focus on when we want to synchronize multiple DACs 5687?

 

thanks in advance for your feedback,

Best regards,

Dounia ELOTMANI

  • 0
    TI__Guru* 79174 points

    Hello Dounia,

    The use of PLL allows you to use the CLK1 clock to multiply up higher for the internal sample clock. This way you do not need to provide the additional CLK2 as your sample clock. The higher the sample clock, the less frequently the harmonics and distortion folds back to the bandwidth of interest. This is the reason why most of the DACs have interpolation filters to allow you to upsample the existing data rate to higher DAC sample rate. This also may help save cost on the FPGA or ASIC.

    For the DAC5687, the most important thing to pay attention is to make sure all the CLK1/CLKC1 clocks are phased aligned to the multiple DACs. This will ensure the PLL in each DAC are seeing the same reference. If this cannot be guaranteed, then synchronization is not possible. 

    For more flexible multi-DAC synchronization, please consider using the family of DAC3282/3 or the DAC3484/2/H84. The FIFO architecture of the DAC family allows multiple DACs to synchronized more flexibly to ensure the same latency throughout each devices. 

    -KH