ADC12DJ3200EVM: RX Elastic Buffer Underflow

Ive fixed the underflow on the upper GTH transceivers by recognizing some incorrect pin constraints:

But I am still getting an underflow on GTH 1, and I have triple checked those constraints.

Nicholas,

Are you using the project from the ADC12DJ3200EVM product folder on the TI website? If so, the constraints should be fine as is. What is the status of LED D0 and D4?

Regards,

Jim

Yes and off

Nicholas,

Both KCU105 LED's D0 and D4 should be on. I am suspecting you may have a clocking issue. Do you have a way of probing the clocks coming out of the LMK04832?

Regards,

Jim

Yes

The Clock coming out of the LMX and going into the ADC and LMK is 1.5 GHz.

The JESD clock coming out of the LMK and going to the FPGA is 150 MHz.

The SYS_REF clock going into the FPGA is 18.8 MHz.

Actually, I may have found the issue. Can you confirm that C50 and C51 are supposed to be populated, not C48 and C53?

Nicholas,

If you are using the LMX for the clock source, this is correct. C50 and C51 should be installed.

Regards,

Jim

Yep, apparently someone had modified this board before I got my hands on it.

So, that got data through for the first time.

The issue that then occurs is link is lost very quickly again after and not regained.

When the link goes down, is the ADC sending constant K28.5 characters? Is the SYNC signal staying low?

Nicholas,

This design was done by a third party vendor for TI that is no longer available. I would highly suggest you look into requesting free JESD204B IP from TI that works with these two platforms. You can request this IP JESD204 rapid design IP by going to the following link:  https://www.ti.com/tool/TI-JESD204-IP.

Currently the JESD204 rapid design IP supports the following FPGA families:

• Xilinx® Virtex UltraScale and UltraScale+
• Xilinx Kintex UltraScale and UltraScale+
• Xilinx Zynq UltraScale+ and Zynq UltraScale+ (Auto)
• Xilinx Artix 7 and Artix 7 (Auto)
• Xilinx Virtex 7
• Xilinx Kintex 7 and Kintex 7 (Auto)
• Xilinx Zynq7000 and Zynq7000 (Auto)

Included with the IP is documentation and example reference designs to allow the user to get up and running quickly.

Regards,

Jim