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DAC8802: Output of DAC8802 Malfunctioning

Vihan Shahu
Prodigy 50 points
Part Number: DAC8802


Dear DAC support team,

We have been using DAC8802 for probing internal controller parameters (FPGA-based controller). After generating the correct clock and CS pulses for the SPI protocol, the rest of the pins: MSB and RS\bar, were given fixed values of 0 and 1, respectively, through FGPA gpios. The LDAC\bar pin was pulled down which should mean the output DAC register should automatically get the input register data. The SDI pin was transferring data corresponding to 2AAA bits with the address of channel A (01). Reference voltage Vref corresponds to 4V.

However, at the output of the DAC stage, we are getting a  -4V analogue value corresponding to all 14 bits high, in both the channels irrespective of data input..

Kindly provide some suggestions as to what could cause both channels to see all 14 bits high. Note that when the ldac is pulled high the output corresponds to all the bits low(0), which follows the datasheet table - 2 on page 13.

Screenshot of the schematic.

Attaching the scope shot of communication frame:

Shot 1:-

Green: SCLK       Red: SDI        Blue: CS

Vref = 4.096, DAC clock frequency 5MHz, Data Value = 2AAAh,

DAC address 01 (DAC A)

Shot 2:-

Green: LDAC/MSB       Red: SDI        Blue: CS

both LDAC/MSB waveforms were same.

Shot 3:-

Green: RS\n       Red: SDI        Blue: CS

Regards,

Vihan

PS: The question was also in another thread. For quicker response, I am starting it as a new question.

  • 0
    TI__Mastermind 19086 points

    Hi Vihan,

    I feel like there is a timing mismatch. Please note that the device latches data on the positive edge of the clock.

    From your timing diagram it seems like A1 and A0 value looks like "00" which is not valid.

    Also what is the status of /RS, MSB and /LDAC bit status when the DAC powers up?

    Can you please double check?

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    Hi Akhilesh,

    Thank you for the response.

    Yes, the first clock is extra but I read on the datasheet that the last 16 bits are only updated in the shift register, so the first '0' would be ignored and '01' would appear as address bits.

    Before double checking, what should \RS, MSB and  /LDAC be at the time of DAC powering up?

    I have configured the FPGA such that MSB and /LDAC are having constant outputs of 0 at the time of DAC power up. The \RS is configured to be 'switched on'  by a hardware switch input. However, even when I hardcoded /RS to be always on, the problem was persisting.

    Additionally, the power-on sequence is such that I am powering on DAC first and then turning on the FPGA after some time. Then I turn off the asynchronous reset switch which allows the SCLK, SDI and /CS logics to appear on the respective lines. Note that /LDAC and MSB are permanently hard-coded to be 0. The /RS is tied to the asynchronous reset switch and transitions from 0 to 1 with it.

    I will check the status at the time of DAC power up again though and share the waveforms.

    Regards,

    Vihan

  • 0 in reply to Vihan Shahu
    Prodigy 50 points

    Hi akhilesh

    I have tried a lot of different stuffs and changed the clock pulses to be exactly 16. Yet the problem persists, could you maybe explain what should \RS, MSB and  /LDAC be at the time of DAC powering up?

  • 0 in reply to Vihan Shahu
    TI__Guru 54833 points

    Akhilesh will respond on Wednesday, when he is back in office.

  • 0 in reply to Paul_Frost
    TI__Mastermind 19086 points

    Hi,

    Just a quick question regarding GND connections. You have 2 GND connections, DGND and AGND. Are they shorted together?

    We need to short these GNDs together for proper functioning of the device.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    Hi Akhilesh, yes they are shorted together. Also, although we are still not getting the required output, I have changed the communication waveform quite a bit. I am attaching it in pdf format.DAC 8802 Issues.pdf

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    As a quick debug, can you make sure that /RS = VDD and MSB = VDD ( no FPGA control)

    If everything is correct, after power up, you should see Vref/2 at output ( we are setting MSB = 1, for mid scale code).

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    HI Akhilesh, just checked, MSB = VDD (No FPGA control) is giving Vref/2 output. [Update: I forgot to keep /RS high. I will check with that]

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    send DAC data as all zeros, with proper address

    Please make sure that /RS and MSB = high ( not FPGA controlled)

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    Hi Akhilesh, I followed up on your advice. 

    1. For the case mentioned MSB = Vdd and /RS = Vdd with no fpga control: Output voltage mid scale value Vref/2 showing during power up.

    2. Sending all zero DAC data with proper address shifts output to Vref, which should not happen. Please see the following image which was taken as a single shot just after the fpga powers up.

    It can be observed that output voltage moves from -2V to -4V (Vref)

    The code given in 1100 0000 0000 0000 binary. So both channels should show the same value. The LDAC is being pulled low after clock cycle is over and then pulled high after about 100ns.

  • 0 in reply to Vihan Shahu
    TI__Guru 54833 points

    AK will take respond after the local holiday.

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    When you did this experiment ( all zero data), I believe both MSB and /RS was permanently tied to high as in hardware control.

    Can you do one more quick check, keep /LDAC low during power up and repeat the same experiment?

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    Hi akhilesh,

    Yes MSB and /RS had been tied to high through hardware and they were powering up with the dac. The fpga was not powered up during that time. In such condition Vref/2 was observed.

    I will repeat the test keeping /LDAC low and update on the output.

    Thanks and regards,

    Vihan

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    I will wait for your update.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    HI Akhilesh,

    Thank you for waiting. Following waveforms were observed:

    In the last figure it can be seen that the output still goes to -Vref from -Vref/2 on both the channels. The input code is 1100 0000 0000 0000 in binary.

    Additional point: /CS signal is zero during/after DAC power-on. It becomes high when FPGA code execution starts.

    Also, I am wondering whether the schematic is itself correct or not hence attaching the schematic again.

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    The fact that you are getting -Vref/2 on power up indicates the schematics is fine.

    Couple of observations from the scope shots.

    1. Why there is lot of glitches on /MSB and /LDAC when the FPGA is powered on?

    2. Can you please share the complete schematics from FPGA to DAC ?

    Also if possible share the layout of the board.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 50 points

    Hi akhilesh,

    Sorry for the delay, was out sick!

    Few updates

    1. The glitches on the MSB and /RS pin was probe issue. They are no longer present. (I had used one ground lead for all the probe pins which increased the loop path).

    2. I replicated the process you described for another DAC ( There was provision for 2 DACs) and it worked! The output is matching the code input.

    Now I need to check for the malfunctioning DAC whether the IC is gone bad or whether there is an issue in connection from FPGA to DAC. I would be sharing the schematic soon.

    Thanking you

    Vihan

  • 0 in reply to Vihan Shahu
    TI__Mastermind 19086 points

    Hi,

    If you are getting the outputs on another board, most likely issue can be bad solder, device gone bad etc. Anyway share the schematics, I will do a thorough check.

    Regards,

    AK