ADC3422: Interface it with a spartan 6 FPGA

Jonathan Navor

Part Number: ADC3422

Hi Team,

Good day! Our customer is asking how ADC3422 can be interface with a spartan 6 FPGA. If possible could you please provide Verilog files or some project for ADC3422?

Thank you so much in advance.

Best regards,

Jonathan

over 3 years ago

0 Chase W over 3 years ago

TI__Mastermind 23760 points

Hi Jonathan,

We don't have any project files available for the Spartan 6 FPGA. The capture board (TSW1400EVM) which the ADC3422EVM interfaces with is an altera. I would suggest the customer ask Xilinx on the best approach on how to implement a 4 or 8 pair LVDS interface (based on whether they want to use the ADC in 1-wire (4 LVDS pairs) or 2-wire (8 LVDS pairs) mode) on the Spartan 6 FPGA. Keep in mind that since this is Serial LVDS (SLVDS), the frame clock (FCLK) is used to indicate the transition/partition between each sample. Also, the data clock is DDR, meaning the data is valid on both the rising and falling edges of the data clock signal.

Regards, Chase

0 Jieru Z over 3 years ago in reply to Chase W

Prodigy 10 points

Hi Chase,

Thank you so much for your suggestion and information! It really helps. Would you mind to share the Verilog files of using ADC3422(interfacing with an altera is okay)? Thank you again and have a great day.

Best,

Jieru

+1 Chase W over 3 years ago in reply to Jieru Z

TI__Mastermind 23760 points

Hi Jieru,

Certainly, they are available online at this link: https://www.ti.com/lit/zip/slwc115

Once you run the .exe, the files should install at this directory: C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\Source Code

Regards, Chase

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ADC3422: Interface it with a spartan 6 FPGA