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ADC12DJ3200EVM: JMODE0, Data Format

Jeremy Patterson
Prodigy 25 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200

I am using the example design for the ADC12DJ3200 JMODE0 connected to the KCU105 board. I am having trouble converting the data to a datastream once I get it into chipscope. I ran the design at 1500 Msps onboard clock like the included tutorial instructs.

Xilinx KCU105 + ADC12DJ3200 JMODE0/JMODE2 Design Firmware: www.ti.com/.../slvc698

Can I get some help understanding how to convert an exported CSV file into a stream of samples?

  • 0
    TI__Mastermind 37960 points

    Hi Jeremy,

    I will have someone look into this for you and get back to you in a few days.

    Regards,

    Rob

  • 0
    Prodigy 25 points

    Can I get an application engineer to perform a data capture on a terminated connection on the Xilinx KCU105 + ADC12DJ3200 example project and help me understand how the conversion from lanes to samples works?

  • 0 in reply to Jeremy Patterson
    TI__Guru* 91947 points

    Jeremy,

    This design was done by a third party vendor for TI that is no longer available. I would highly suggest you look into requesting free JESD204B IP from TI that works with these two platforms. You can request this IP JESD204 rapid design IP by going to the following link:  https://www.ti.com/tool/TI-JESD204-IP.

    Currently the JESD204 rapid design IP supports the following FPGA families:

    • Xilinx® Virtex UltraScale and UltraScale+
    • Xilinx Kintex UltraScale and UltraScale+
    • Xilinx Zynq UltraScale+ and Zynq UltraScale+ (Auto)
    • Xilinx Artix 7 and Artix 7 (Auto)
    • Xilinx Virtex 7
    • Xilinx Kintex 7 and Kintex 7 (Auto)
    • Xilinx Zynq7000 and Zynq7000 (Auto)

    Included with the IP is documentation and example reference designs to allow the user to get up and running quickly.

    Regards,

    Jim