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AFE5832LPEVM: LVDS capture code for Xilinx ultrascale+ family

Rouzbeh Molaei
Prodigy 95 points

Part Number: AFE5832LPEVM
Other Parts Discussed in Thread: AFE5832LP

Dear TI,
I am Rouzbeh Molaei from UT Dallas. I am working on the wearable ultrasound sensor project. I bought TI AFE5832LP EVM board (AFE5832LPEVM Evaluation board | TI.com) to send LVDS data to a Xilinx Zynq Ultrascale+ FPGA. I bought the TI FMC-ADC adaptor (https://www.ti.com/tool/AFE5832LPEVM) to connect TI AFE5832LP EVM to Xilinx US+ FPGA (ZCU104). I need the LVDS capture code for Xilinx US+ technology to see the LVDS output of the AFE5832LP EVM. The Xilinx Ultrascale+ FPGA clocking design is different compared to it's predecessor. Could you please help me with this code to see the LVDS output of the AFE5832LP EVM board? 

Thanks,
Rouzbeh
  • 0
    TI__Expert 6805 points

    Hello Rouzbeh, 

    Apologies for the delay. E2E was offline for a few days for maintenance. We'll need a couple days to catch up. You'll have a response within 72 hours. 

    Kind regards,
    Nick Z

  • 0 in reply to Nick Zahabizadeh
    Prodigy 95 points

    Dear Nick,

    Thanks for your message. I will wait for E2E to respond to my appeal.

    Thanks,

    Rouzbeh

  • 0 in reply to Rouzbeh Molaei
    TI__Expert 6805 points

    Hi Rouzbeh, 

    Responding to both posts: Our SME with these devices are still catching up. In 48 hours we'll have a response. 

    Kind regards,
    Nick Z

  • 0
    TI__Expert 7140 points

    Hi Rouzbeh,

    Sorry for the delay.

    Typically, we assume our customers to implement the FPGA codes since they have generations of products and lot more expertise in the FPGA firmware developments. We typically provide the LVDS timing diagrams and customers use the information from the datasheet to implement their capture solution.

    Since, we are not experts in FPGA code developments we either use 3rd party to develop the firmware or develop very basic codes to verify device functionality. Same is the case with AFE5832LP device.

    Our EVM capture solution is based on TSW1400 card which uses Altera FPGA and the firmware was developed by 3rd party. We do not know the technical depth in the implemented FPGA firmware.

    We worked on Swaroop design as well, where we had used Xilinx Artix-7 FPGA and I hope you already have that firmware from the MSS server. If not then, I can help you get that code. That firmware must be most similar to Xilinx US+.

    Unfortunately, we do not have further engagements with the 3rd party vendor anymore and most of our developers on that have also left the team. So, it is very difficult for us to support firmware on the Xilinx Ultrascale+ FPGA since we do not have any expertise.

    I also checked internally within my team if we are able to support this development but unfortunately, and we cannot because of the necessary expertise & bandwidth requirements.

    I think you can reach out to Xilinx to provide you some example implementation of the LVDS capture in US+.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    Prodigy 95 points

    Dear Abhishek,


    Thanks for your response. I would appreciate it.

    It was helpful. I would definitely reach out to Xilinx to get some examples of LVDS capture code for US+.

    Thanks,
    Rouzbeh