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ADS1278: non-linearity questions with different sample rate

Part Number: ADS1278
Other Parts Discussed in Thread: INA2128,

Hello,

  We use the ina 2128 chip to amplify the 24 channels signal  from the pressure sensor and then input the signal into the ads 1278 chip to get a digital signal.

The temperature characteristics of the ads 1278 chip are tested experimentally, and the other experimental conditions are the same, input a constant signal, test the output of the ads 1278 chip with temperature changes at 512 fps and 50 fps respectively, the output signal is shown in Figure 1 below, Figure 2 below. It can be found that the non-linearity of the output signal is significantly improved when the sampling frequency is reduced.

Is there any way to achieve a better linearity at 512 fps?

Best regards

Kailyn

  • Hello Kailyn,

    The ADS1278 has a lower input impedance at higher sample rates, which could cause a shift in the INA2128 output over temperature.  The reference input current also increases with higher sample rates, which could also cause a shift in the reference output voltage over temperature.

    If you could provide the schematic that shows the INA2128, ADS1278, and the reference, I will review to see if there is anything that can be changed to help improve performance at 512sps.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hi Keith,

    Thank you for your reply.

    Best regards

    kailyn

  • Hi Kailyn,

    Can you also provide the frequency for the CLK input?  This frequency effects the input impedance for both the analog inputs and the reference input.

    Quickly looking at the schematic, I think the REFP buffer should be changed to a higher bandwidth device to fully support the reference input impedance for the 3 ADS1278 ADCs.

    This amplifier is marginally stable with the 1uF load capacitance, and is not likely able to drive 3x ADS1278's properly.  The below circuit will work well, but may be more than is needed in this case.

    I will provide additional comments once I know the CLK frequency that is used in the design.

    Thanks

    Regards,
    Keith

  • Hi Keith,

    Thank you very much for your reply. The input frequency is 1.3125MHzm, and ADS1278 works low speed mode.

    Best regards

    kailyn

  • Hello Kailyn,

    Thank you for the additional information.

    I believe the most likely cause for the gain error difference is the reference circuit that I had mentioned before.  The reference input current for 3 ADS1278 ADC's operating with a CLK frequency of 1.3125MHz in Low speed mode will be around 5mA, with peak current in the 10's of mA.  I suggest updating this buffer circuit.  The below circuit will work well and has been verified with different ADC's, but may be more performance than needed.

    Another option is to use the below circuit.  This circuit only requires a single amplifier, but will have higher offset voltage drift of 1.5uV/degC typical, which is still very good performance.

    Other comments regarding the schematics:

    1.  The AGND and DGND pins of the ADS1278 should be connected to the same ground plane and not through an inductor or ferrite.  Ideally, all grounds can connect directly to the thermal pad with multiple vias directly into the ground plane.

    2.  DRDY pin is an output that indicates when new data are available to be read from the device.  The host MCU monitors this pin through polling or an interrupt, and reads data when DRDY=LOW.  Since only 1 DRDY pin is connected to the host MCU (AD2, pin 29), it is important that all ADCs are synchronized, following Figure 73 in the datasheet.

    3.  Please insure that bypass capacitors 0.1uF+10uF are as close to the AVDD, DVDD, and IOVDD pins as possible for each device.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hello Kailyn,

    Please let me know if there are any additional questions.

    Regards,
    Keith