Hi Team,
VDD and VIO same supply 3.3V
CS has 10K to VDD
No MOSI from chip to be able to read
REF to 2.2uF cap to gnd
SPI clk mode 1
after a reset the default register set seems to be enabled thru the SYNC reg addr 02 - 0xFF00 (async)
Gain reg is at reset all zeros -- I also tried setting it.
I set the DAC reg (8-F) to various 12bit value and never see the output turn on. (sync reg states that value is pushed out auto to the output reg.
I have tried various ways with the FSBO bit set/unset but shouldn't matter as there is NO SDO
All 24bit accesses are continuous with no byte gap
Hoping for your assistance.
Thank you.
-Mark
