• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 47 subscribers
  • Views 226 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE58JD32LP: DCLK output clock offset

Hailey Chen
Expert 3100 points
Part Number: AFE58JD32LP
Other Parts Discussed in Thread: AFE58JD32

Hi, team:

    My customer use AFE58JD3LP  in their ultrasound, 

    The DCLK of AFE58JD32 is output by AFE 480MHz, but the measured clock offset is very large, more than 6%. Minimum :448MHz, maximum: 515MHz.mean：480Mhz

    The frequency of the Gaussian distribution centered on 503M,485M,469M,457M

    The customer tests the ADC clock is 80Mhz ，Each chip uses 8 pairs of LVDS, From the test results, the ADC clock frequency is OK, but the DCLK offset is very large

    Did you encountered similar issue, Could you give some debugging suggestions？ 

  • 0
    TI__Expert 6980 points

    Hi Hailey,

    Thank you for reaching out.

    Let me gather the information about the expected variation in DCLK frequency. To me, it looks on the higher side, but confirmation from the design team would be better before from the sim results while conveying to the customer.

    Please allow me some time to check on the same and I will get back to you either by tomorrow or latest by Monday.

    Thanks & regards,

    Abhishek

  • 0
    TI__Expert 4890 points

    Hi Hailey, 

    This is not expected. Some pointers for debug - 

    1. Can you share the full configuration of the device? Is it 16ch, 80MSPS, 12bit. Why are you having 8 pairs of LVDS, should it not be 16 DOUTs, 1 DCLK, and 1 FCLK?

    2. Can you share some waveforms to illustrate the issue? Can you confirm that your oscilloscope and probe has the required bandwidth (>1GHz) to perform these measurements. Also, this measurement must be with differential probes (at OUTP and OUTM in the below diagram) with 100-ohm external termination. 

    3. Can you apply 'deskew' test pattern, observe a DOUTx, DCLK, and FCLK, and share waveforms?

    Thanks, 

    Karthik