• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 46 subscribers
  • Views 695 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS52J90: ADS52J90 in JESD204b mode

Alex Swensson
Prodigy 10 points
Part Number: ADS52J90


ADS52J90 .in JESD204b mode 

Please tell me how can I enable test pattern mode(ramp, for example). Thanks.
  • 0
    TI__Expert 4920 points

    Hi, 

    All test patterns described in the LVDS Test Pattern Mode section can be set, even with the JESD204B interface. These test patterns serve as transport layer test modes for the JESD interface. These test patterns can replace the normal ADC data going into the JESD204B link layer.

    So, use PAT_MODES (Register2<9:7>) for setting these test modes. 

    Thanks,

    Karthik

  • 0 in reply to Karthik Nagabhushana
    Prodigy 10 points

    Hi,

    Thank you very much sir.

    I've got one more question:

    how to separate even and odd adc sample in 32-input mode ?

    Thanks,

    Alex

  • 0 in reply to Alex Swensson
    TI__Expert 4920 points

    Hi Alex, 

    You will have to use the TX_TRIG signal to synchronize the device as given in section 8.3.4 in the datasheet. Then, there will be a deterministic delay between your TX_TRIG and the first odd sample. Refer to the ADC latency and JESD LATENCY in the datasheet for the exact delays. 

    Note that the device has only 16 ADCs. So, in the 32-input mode, there is a half-clock sampling delay between the odd and even channels - 

    Thanks,

    Karthik