ADS114S08: What's the VOL (Logic output level) of GPIO_low when IOL = 10uA for ADS114S08 and ADS124S08's GPIO?

Hello Hao,

Both the table and the graph are correct, but there may be some misunderstanding in interpreting what is being shown.  The electrical characteristics table is showing the device response for a specific condition.  The condition is with a 1mA loading at 25 deg C and these numbers are the guaranteed specifications for that operation. 

Figure 39 graph is showing typical GPIO current over various temperature ranges and different current loading.  Figure 39 was added because many customers connect the GPIO to devices not specifically logic devices.  There is a desire to know and understand the behavior of the analog GPIO in higher than 1mA loading conditions.

A complimentary MOS device (CMOS) has an active push-pull driver stage that when operating at a logic high turns on the PMOS device connected to the AVDD supply while the NMOS device is turned off.  A logic low turns off the PMOS device and turns on the NMOS device to AVSS.  In any case there will be some inherent resistance in the MOS devices.  The higher the current the greater the loading across the MOS resistances which will lower the logic high voltage and increase the logic low voltage.

The outcome of the loading is shown in Figure 39 where when little current is being drawn, the logic low is close to 0 (AVSS is connected to AGND in this case) and when the loading is high the output voltage increases as the voltage drop across the NMOS resistance also increases.

A standard CMOS device input will have only a small loading affect.  The result is the voltage for logic high is much closer to AVDD and logic low is much closer to AVSS.

As to differences between the graphs and the table remember one is typical and the other is guaranteed.  There will be some lot to lot and device to device variation.  The MOS devices may vary some with respect to resistances when the MOS device is turned on.  The effect of the MOS resistance will depend on the current loading.

Best regards,

Bob B

Hi Hao,

The guaranteed value is with the conditions specified in the datasheet.  There should be no need to further guarantee performance at less currents.  The reason for this is by basic circuit analysis.  Consider the GPIO as analog switches with some value of resistance associated with the RON value of the switch.  When turning on the low-side switch there is a path to AVSS (AGND with unipolar supplies).  We can calculate the worst case switch resistance for 3.3V AVDD as being Vol (max) divided by the 1mA current from the guaranteed specification value.  The result of ((3.3V * 0.2) / 1mA) is equal to 660 Ohms.

If we now calculate for 10uA we see a voltage of 10uA * 660 Ohms which equals 6.6mV.  This is much closer to 0V and follows the graph in Figure 39.

Best regards,

Bob B