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ADS1299-6: Cascading ADS1299's not working with one of the chips

Part Number: ADS1299-6
Other Parts Discussed in Thread: ADS1299

I have 2 ADS1299's connected to the same SPI lines, except for chip select pin. I have modified the first ADS's CONFIG1 register so it outputs a clock signal via CLK pin, and this chip's CLK_SEL pin is tied to DVDD with a 10k resistor. 

The second ADS has does not have a DRDY pin, and no START pin either and it's CLK_SEL pin is tied to ground via a 10k resistor. after outputting the clock signal from the first ADS, I am trying to read registers from the second ADS, but it's not giving back correct values. I have tried turning the clock from the first ADS on and off and reading from the second ADS, which shows no difference either, except for sometime rather than showing just 0's it shows some random 1's as well.

I checked the clock and it's at 1.78 MHz, which is below what the internal oscillator should be making, but still is within the range of the required CLK frequency according to the datasheet.

I follow the process that is: 

  • turning device 1 CS low;
  • modifying CONFIG1 so CLK is connected to device 1's oscillator;
  • turning device 1 CS high;
  • turning device 2 CS low;
  • reading registers.

Am I missing something fundamental here? 

  • Hi,

    Appreciate for your detail description.

    Are you trying to use the Cascaded Mode for two ADS devices and share the CLK pin&line between the two ADS?

    It seems you set/use internal clock(CLKSEL=1(DVDD) CONFIG1.CLK_EN BIT=1 for the 1st ADS and  use external oscillator clock for 2nd ADS(CLKSEL=0(GND), which takes in the CLK output from 1st ADS.

    May I ask refer to data sheet page 65 Figure 70. Multiple Device Configurations, which way did you connect the two ADS to master/host?

    Similar question, may I ask how the START, /DRDY, /CS, SCLK, DAISY_IN and DOUT from both chips are connected?

    Is DAISY_IN pin used in any chip?

    Internal oscillator clock frequency should be around 2.4MHz  +-/- 2.5%

    May I also ask, have you or could you try read the 9.6.1.1 ID: ID Control Register (address = 00h) (reset = xxh) of both chips individually? do they both return the correct reset values shown in 9.6.1.1 ID: ID Control Register (address = 00h) (reset = xxh)?

    Do you mind if you could try provide another pin connection from the host and connect such pin to the /DRDY of the chip you think not working, and then communicate with the not working chip same way as the working chip to see how it works?

    Thanks

  • Hi,
    Since I did not hear back from you, I believe my suggestions answered your questions.
    I will close this post and if you have any pending questions, feel free to post them here or open a new thread.
    Thanks and have a great day!