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ADC3662: DCLK timing requirements and data valid specification

Thomas Behnke
Prodigy 60 points
Part Number: ADC3662

Dear All!

Chapter 6.8 (page 13) of ADC3662 data sheet (SBAS991A) defines timing requirement for tCD (DCLK rising edge to output data delay) and tDV (data valid).

For our implementation we assume tCD is valid also for falling edge of DCLK. In addition data valid tDV is also applicable for both phase of DCLK.

Can you confirm or clarify?

best regards

Thomas