Dear TI Team,
I want to know about the output update rate for four channels in parellel for DAC 8775. It seems it works fine till 1 kHz after that it is not worked properly and I saw some cliiping in signals.
Hi Lucas and Katlynne,
Here's some more information:
The customer is using spi clock 8 MHz, slew rate disabled as VPOS and VNEG are supplied externally and Output enable settings. The problem is that they cannot achieve a data rate more than 1KHz for all four channels.
The image below shows the channel 1 and 3 comparison.
The image below is for channels 1 & 4. the offset with higher frequency like you can see from the picture 1 & 2. The voltage range is configured from 0 to 10V.
The fall time is always doubled or tripled in case of frequency more than 1 KHz. the DAC is set up in sequence before the ramp loop and only 3 bytes are transferred for setting the DAC data register.
And just to verify, are you using the configurable slew rate feature? (Bit 4 of Configuration DAC register or on TI's DAC8775EVM GUI)
They are not using the configurable slew rate in Config DAC register. they are writing 0x1001 in the config DAC register (to select output enable and output voltage from 0-10V).
The customer is enabling the internal reference in reset config register(0x0010) before configuring DAC. After configuring DAC, and selecting the DACs(0x01F0) and Writing into the DACs using internal reference(5V) and applying +10 to VPOS_IN and -10V to VNEG_IN.
I hope this helps.
Regards,
Marvin
Hi Marvin,
The externally supplied VPOS_IN and VNEG_IN should have a decent amount of headroom and should be closer to ±13 V.
These are the expected output rates for the 10 V range (about 12 µs), what output load is the customer using?
Thanks,
Lucas
