• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 285 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC60501: SPI configuration

Sean Song
Intellectual 1640 points
Part Number: DAC60501

Hi Expert,

Our customer use DAC60501 in their system.

They want to ask some questions,

1. SPI configuration:
There is no direct description in the datasheet, I guess from the graphics:
kLPSPI_ClockPolarityActiveLow;
masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;

2. LSB or MSB;
There is no description found in the Datasheet, please help to confirm.

3. Synchronize update settings;

Synchronous updates should be set to 1; am I right?

But this sentence also says that the asynchronous mode is to update immediately, which is a bit confusing;

4. about DAC-DATA；

Regarding this data format, can you be more detailed, LSB/MSB, 0 bit is the lowest bit, 11 bit is the highest bit, because we are using 60501.

Thanks

Best Regards

Sean

  • 0
    TI__Mastermind 25283 points

    Hi Sean,

    Illia will have a chance to review this and get an answer to you tomorrow. 

    Best,

    Katlynne Jones 

  • 0 in reply to Katlynne Jones
    TI__Intellectual 1640 points

    Hi Expert,

    Do you have any update?

    Thanks

    Sean

  • 0 in reply to Sean Song
    TI__Intellectual 1585 points

    Hello Sean, 

    I apologize for delay. 

    1) The initial idle state of a clock could be either High or Low, hence it is represented that way on the diagram. As Sync pin pulled low however, the data is rising edge triggered, so in order to transmit first bit, when Sync goes low, clock needs to go high, which will initiate communication sequence. 

    2) While the data is sent out MSB first to LSB, this is something that is configured through microcontroller when SPI mode is chosen. 

    3) In asynchronous mode, whenever there is data written to DAC buffer, it automatically updates the DAC output immediately, while in synchronous mode, in order for DAC to update its output a LDAC trigger event needs to happen. Please refer to section 8.3.1.2 on page 21 of the Datasheet for a better detail. 

    4) DACx0501 is left aligned, meaning that most significant bit is always bit 15. In 16-bit version, all 16 bits are valid data, in 12-bit version bit 0, bit 1, bit 2, bit 3 are don`t cares, and usually are zeroes, hence needed to be truncated. 

    Did this answer your questions? 

     Thank you, 

    Illia Volkov