DAC38J82: DAC gives an error - read_empty : FIFO is empty

Evgenly,

Is the FIFO empty error reported for every lane? In most cases, this error is caused by an issue with either the sample clock or SYSREF not at the correct frequency.

What is your SYSREF frequency? What value is used for "K"? Make sure both the FPGA and DAC are using the same K value. 

Is SYREF AC or DC coupled going to the DAC?

Regards,

Jim 

Jim,

yes, both lanes has the same error. Clock is 262.144 MHz and SYSREF is 6.5536 MHz, K=10, SYSREF is DC coupled.

Evgenly,

What is the interpolation factor you are using?

Regards,

Jim

Jim,

interpolation factor is 4.

Evgenly,

If the DAC is sampling at 262.144MHz and the interpolation is set to 4, the FPGA data rate is 262.144 / 4 = 65.536MHz. The lane rate is then going to be the data rate * 20 = 1310.72Mbps, not  5242.88Mbps as you are reporting. Using your settings, but with a lane rate of 1310.72Msps, I have the DAC38J82EVM running using the attached register settings. See how these settings compare to yours.

Regards,

Jim

LMF_2221_RX0_RX2.cfg

Jim,

doesn't the interpolation affect the DAC output rate?
Our FPGA data rate is 262.144 MHz, not 65.536 MHz, the lane rate is 262.144 * 16 * 10/8 = 5242.88 Mbit/s, the interpolation is set to 4, and therefore DAC output rate = 262.144 * 4 = 1048.576 MSPS.
Our DACCLK = 1048.576 MHz

Evgenly,

You mentioned the DAC clock was at 262.144MHz so I assumed this was the sample clock. Are you using the internal DAC PLL to create the 1048.576MHz clock you are now mentioning?

Regards,

Jim

Jim,

yes, we use internal L-band DAC PLL to create the 1048.576 MHz clock.

Evgenly,

Here is the new config file and GUI settings I used to duplicate your setup. No errors were reported and DAC output was correct. Are you tuning the DAC PLL to get it to lock?

Regards,

Jim

Lane_5242.88_Fs_1048.576.cfgDAC38J82_PLL_RX0_RX2_LMFS_2221.pptx

Jim,

the DAC PLL is always lock, alarm_from_pll = 0 (config108, bit 0). The DAC PLL is out of lock when pll_vco = 33 (100001), as in Lane_5242.88_Fs_1048.576.cfg file. The DAC PLL is lock when pll_vco = 36 (100100) or 37 (100101).
Also the DAC PLL is out of lock if lockdet_adj = 000 or 001 (config49, bits 15:13), the DAC PLL is lock when lockdet_adj = 010 or 011.
The memin_pll_lfvolt is 011 (config49, bits 2:0). The SERDES PLL is always lock too, alarm_rw0_pll = 0 (config108, bit 3).

I found that SYNC is always 1, even when SYSREF comes.

Evgenly,

Are you using lanes RX0 and RX2? Just want to verify this. The PLL lock settings will vary from part to part so my settings may not always work with yours. Does SYNC ever go low when you start the link initialization and then go high after CGS has completed? Can you change the input clock from 262.144MHz to 1048.576 and disable the PLL to see if this is your issue? 

Regards,

Jim

Jim,

"Are you using lanes RX0 and RX2? Just want to verify this."

- Yes, we use lanes RX0 and RX2.

"Does SYNC ever go low when you start the link initialization and then go high after CGS has completed?"

- SYNC is high all the time, even after power up.

"Can you change the input clock from 262.144MHz to 1048.576 and disable the PLL to see if this is your issue?"

- No, unfortunately, I can't change input clock from 262.144 to 1048.576, because input clock is from LMK04828, which has VCO0 (2370...2630 MHz), VCO1 (2920...3080 MHz) and output divider (1...32). LMK Fin pin is not connected.
So, I changed the settings for 5000 Mbit/s speed, and when input clock equal 1000 MHz. With DAC PLL disabled, the same result, the DAC gives only one error - read_empty : FIFO is empty. PRBS test was successful.

Evgeniy,

Trying running with the NCO only to see if you get an output tone. This will verify the clock is correct, power is OK, and SPI is working properly. Attached are register settings to use for this after you have configured the DAC and the PLL is locked.

Regards,

Jim

8130.nco_only.cfg

Jim,
there is an output tone at the output of the DAC, the frequency corresponds to the NCO value.

Evgeniy,

You must get SYNC to toggle for the link to come up. Make sure you are following all steps, especially 13 and 14, of the Initialization section shown in section 8.3 of the data sheet.

Regards,

Jim 

Jim,

in my case SYSREF is DC coupled. But, fortunately, for single DAC/ADC SYSREF is not needed so we just shut it off.

Many thanks!