Hi David,
The amplifier will have to drive a 1-uF capacitor (without being unstable), be able to provide a max of 5mA average current, and be low-noise.
I pulled up the EVM schematics and I see this particular circuit which you can use as a starting point - U31 opamp is OPA4353 which meets all the above requirements.
Thanks,
Karthik
Hi David,
Yes, I did.
Firstly, I would recommend for you to use the internal reference circuit. As explained in the datasheet (Figure 93), board and device-packaging parasitics can degrade the SNR performance. Is there a compelling reason why you would want to use the external reference mode? The internal reference circuit gives a gain matching of ±1.5% across devices.
In case you do plan to use the external reference mode, to first-order, you can model the load requirement on REFT and REFB as a current impulse every clock edge. The average current drawn for max sampling speed (200MHz) is then 5mA. For a lower sampling speed, the current will scale down linearly.
Now, for the driver circuit mentioned in this thread above, the impulse current is provided by a big 1uF capacitor and hence the voltage ripple is very small. Also, the DC current to the 1uF capacitor is provided by the opamp. So, a lower closed-loop bandwidth of the driver (opamp + feedback network) is acceptable since it is meant to only provide the DC current.
Finally, the driver circuit must be stable while driving a 1uF and you might be right on the location of the 100pF. I suggest that you to do a PSPICE simulation using an OPA4353 model here where you can check i) stability of the loop by performing an AC simulation, ii) voltage ripple on the 1uF by modeling REFT/B load currents as a current-impulse-train by performing a transient simulation.
Thanks,
Karthik
