TI-JESD204c-IP Error generated from encrypted envelop

Hi Rodrigo,

Kindly send us a summary of the changes that you have made. Are you able to run a simulation with the design? This will help identify if these are related only to synthesis. 

Regards,

Ameet

Hi Ameet,

My design requires only 2 Rx lanes and should fit in the AC701 Artix-7 kit. Based on these requirements I've modified the project part, I've changed the GTX transceivers to a pair of Rx GTP and I've upgraded all the IPs to the Vivado 2022.1.2

Besides that I've updated the ILA IPs and RTLs to fit the two GTP lanes.

Regarding the simulaion I've got the message below when I try to run it. I didn't spend much time to try identify this issue.

Thank you,

Rodrigo

Hi Rodrigo,

The GTP's would have moved you to a 32 bit lane width. Kindly confirm if you updated the IP parameters to reflect this. In addition the transceiver wrapper file may have needed updates, if the transceiver entity was modified by the wizard.

Regards,

Ameet

Hi Ameet, yes, I've updated the parameters to reflect the lane width change as well as the updates in the wrapper file.

If you prefer I can share the design with you.

Thank you,

Rodrigo

Ameet,

One more information. If I remove the IP instantiation (TI_240c_IP) of my design I can synthesize it without errors.

Regards,

Rodrigo

Rodrigo,

Are you still needing assistance with this issue?

Regards,

Jim