Other Parts Discussed in Thread: ADC32J45
I have a ADC32J45EVM development board connected to a KCU105 FPGA development board. I want to read sample data with the JESD204B interface, but I can not get the link to establish CGA/ILA. My LMFSK is 2,2,2,2,10. I want 160MSPS. I am using subclass 2. When I start the FPGA everything on the receiver side is initialized, locked, and error free, but it waits forever with no CGA/ILA. If I manually tell the ADC to send alignment characters (using the GUI) the FPGA receives the K characters but never goes into ILA. I suspect the SYNC~ interface is to blame. When I measure the voltage on the SYNC~ pins it is at the correct level and behaves as expected (falling edge when link resets).