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ADS1675: 2MSPS

Andrea Fontana1
Prodigy 210 points

Part Number: ADS1675

Hi Support Team,

Correct me if I'm wrong, but the only way to have 2MSPS with ADS1675 is with the following settings:

Fclk = 16 MHz

DRATE = 101  => Fclk/8 = 2MSPS

With DRDY timing = 1/2MSPS = 0.5 us

and Fsclk = 16Mhz x 3 = 48 Mhz, which give me a correct 48 Mbit/s (2x24 bit, so 2MSPS)  with one sclk for one data bit.

If I stay with Fclk = 32 Mhz

DRATE = 100 => Fclk/16 = 2MSPS

DRDY timing remain 0.5 us

but Fsclk = 32 MHz x 3 = 96 MHz  ... this would mean that I will have 2 clock pulse for one bit data ?

Thanks

Andrea

  • +1
    TI__Guru 51870 points

    Hello Andrea,

    I apologize for the late reply; I have been on vacation for the past week.

    You can use either approach for a 2MSPS output data rate.  Fclk=32MHz will generate an Fsclk=96MHz.  Using DRATE=100 will provide an oversampling of 16, which reduces input referred noise and provides a larger dynamic range of 104dB (low latency filter) compared to DRATE=101.  In this mode, the first 24 SCLKs after DRDY rising edge will be the 24b conversion result, and the remaining 24 SCLKs should be ignored.

    You can also set Fclk=16MHz and use DRATE=101, which will also provide a 2MSPS output data rate.  In this case, the dynamic range will be 103dB (low latency filter) and you will have exactly 24 SCLKs per data output period (Fsclk=48MHz).  In this case, all SCLKs will be used to read the conversion result.

    I see that you reposted this question; I will close out the first e2e thread.  Please feel free to ask additional questions on this thread.

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications