ADS1291: ADS1291 Datarate and ECG Noise

Hi,

May I ask if you happen to have/use an evaluation kit/board(EVM)?

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For, "Only use the SCLK pin, However, SCLK is SPI Clock, I know that it is not involved in chip clock(right?)"

Depending what you mean by "involved"? in general, yes, but there are some constraints for SCLK to be met - e.g.

datasheet page 28 "SCLK can be only twice the speed of fCLK during a register read or write, see section on sending multi-byte commands."

page 41, "For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of bits of resolution, and output data rate. The minimum speed can be calculated with Equation 9."

"

Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. Equation 9 assumes that there are no other commands issued in between data captures. SCLK can only be twice the speed of fCLK during register reads and writes. For faster SPI interface, use fCLK = 2.048 MHz and set the CLK_DIV register bit (in the LOFF_STAT register) to '1'.

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and page 44, Figure 48. Settling Time, 

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Figure 48 shows the timing diagram and Table 13 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Refer to Table 10 for the settling time as a function of tMOD.

tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1.

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and page 49

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8.5.2.8 SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this command, but the following command must wait for 4 tCLK cycles.

"

"

8.5.2.10 Sending Multi-Byte Commands

Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs. Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to multiple bytes.

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Page 48

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8.5.2.7 RDATAC: Read Data Continuous

RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a SDATAC command must be issued before any other commands can be sent to the device. There is no restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC opcode command should wait at least 4 tCLK cycles. RDATAC timing is shown in Figure 52. As Figure 52 shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. To retrieve data from the device after RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 52 shows the recommended way to use the RDATAC command. RDATAC is ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to be re-configured.

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So, as you can see CLK and SCLK do not have to be dependent on each other, but, there are constraints and restrictions need to be met for SPI to work properly; not sure whether this means "involve" to you?

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For "So basically, do you mean that the internal clock can be supported up to 128KHz?"

datasheet, page 9, "Internal oscillator clock frequency Nominal frequency 512 kHz"

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Not sure about your statement or question for "Then, is the DATA RATE value set by CONFIG1.DR2~DR0 applied?"

but, 
Ex.

CONFIG1 = 0x02(500SPS) <- this is correct; DATA RARE is 500 samples per second with this setting.

= 500Hz  <- I wouldn't call it 500Hz to avoid confusing with the modulator frequency used by the ADC.

15000 data at 30 second measurement <- this is about right if the measurement you are referring means the digitized data point out put from the ADS, not the amount of the data that ADC is sampling. 

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For "what role CLK_DIV plays."?

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8.3.4.3 ADC ΔΣ Modulator Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a secondorder modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 4 or fCLK / 16, as determined by the CLK_DIV bit

"

"

The modulator must be clocked at 128 kHz, regardless of the external clock frequency. Figure 32 shows the relationship between the external clock (fCLK) and the modulator clock (fMOD). The default mode of operation is fCLK = 512 kHz.

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In other words, If you use internal clock(i.e. 512kHz) and don't use external clock, you don't need to worry about Figure 32, and follow the instruction "fCLK = 512 kHz and set CLK_DIV = 0 "

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I think right now, it's early to say what are showing on the plots.

Let's make sure above are clear and set properly first and then, try read some internal test signals.

May I ask are you able to read the "8.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h)" correctly?

And, are you or will you use any ECG simulator?

and, also, have you compared the SPI signal waveforms on your board(assuming) with the SPI signal waveforms on the evaluation kit/board(EVM)? 

Thanks