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Original question:

DAC39J84EVM: change/add reference clock to work in combination with ADC12DJ3200

DAC39J84EVM: change/add reference clock to work in combination with ADC12DJ3200

Vaibhav Jain
Prodigy 180 points
Part Number: DAC39J84EVM
Other Parts Discussed in Thread: ADC12DJ3200EVM, , LMK04828

Hi ,

This is in continuation with the previous question asked by Francesco Raffaelli, of changing reference clock of DAC39J84EVM to 100 MHz, which is currently 122.88 MHz, to match the clock reference of the ADC EVM provided by the CVHD-950-100.000 oscillator (100 MHz reference) . This is done by physically modifying the DAC39J84EVM and place CVHD-950-100.000 instead of Y1, which is currently CVHD-950-122.880. After doing these modifications, we were testing the DAC by sending a 100 MHz sinusoidal pulse through the DAC (screenshot attached) and sending DAC output directly to ADC12DJ3200EVM. The expected output from ADC was a 100 MHz sinusoidal pulse but we recorded a 25MHz sinusoidal pulse (FFT spectrum attached with this message). This might be due to the changing of reference clock of the DAC (to 100 MHz), but GUI still working on the previous reference clock (122.88MHz). Is there a way to rectify this and would this be a hardware change or change in the settings of GUI?

Thanks for your help and looking forward to your response.

Sending 100 MHz sinusoid with DACFFT of received spectrum from ADC( 25MHz sinusoid pulse)

  • 0
    TI__Mastermind 23550 points

    Hi Vaibhav,

    The software on the DAC side should still be fine. The only changes will be related to the LMK04828 settings so calculating new M and N dividers will be required. Can you let us know the mode you want to operate the DAC (LMFS, interpolation, sample rate, etc) and I can help out with the divider calculations if needed.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 180 points

    Hi Chase,

    Thanks for the quick response and help with the calculations. Regarding the mode of operation for DAC,  we are planning to send amplitude modulated (different amplitudes in each pulse whose values come from gaussian distribution)  square pulses at 100 MHz from two channels of DAC and trying to recover them in ADC by connecting output channel of DAC directly to the input channel of the ADC. We are using Onboard Clock option on the DAC GUI and our major goal is to recover the symbols sent with as high DAC Output rate as possible such that the symbols recovered at ADC  are with minimial distortion. We are adjusting the Number of SerDes lanes and interpolation accordingly to get the highest possible DAC Output rate with the condition that distortion should be minimal at the ADC. The current settings are displayed in the screenshot attached below. What mode would DAC be in under these settings? Do we require any more information to ascertain the mode of DAC?

    Thanks again for your help in these regards.

    DAC settings

  • 0 in reply to Vaibhav Jain
    TI__Mastermind 23550 points

    Hi Vaibhav,

    The screenshot above is sufficient. I was just curious about LMFS, interpolation factor, and sample rate primarily. Before we get into calculating new clock details, let me first clarify one thing, I notice that the DAC is programmed for interpolation by 4, meaning the incoming data rate from the FPGA should be the DAC sample rate / 4. In the image above, the DAC is sampling at 1474.56 MSPS but the FPGA has generated a 100 MHz tone under the assumption that the DAC input rate is 1454.76 MSPS, but it is not and therefore the sample will show at 1/4 the speed. This is why the output is showing as 25 MHz rather than 100 MHz. If you simply change the Data Rate (SPS) field in HSDC Pro to match the actual data input data rate (368.64 MSPS) and press Create Tones again, the DAC output will now be 100 MHz.

    Next, about the clocking changes. When we change the reference oscillator to the LMK04828, this directly affects the PLL2 input reference and therefore these settings are what need to be adjusted. On the PLL2 Configuration page, if you modify the highlighted settings to match the below image, the VCO1 should lock at 3 GHz (PFD input frequency = 100MHz). Leaving the clock output dividers as-is will result in the DAC sampling at 1.5 GSPS rather than 1.45476 GSPS. The DAC input data rate (and the FPGA output data rate) will now be 375 MHz. The FPGA reference clock will now be 187.5 MHz. I can create a configuration file for you which sets the EVM up for this mode. Let me know if this is needed.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 180 points

    Hi Chase, apologies for the late reply. Would it be possible to send a configuration file for the same. I have tried to change it to the highlights settings but the error persists. A big thanks for your help with this matter. Also, how would I load this configuration file in the DAC GUI?

  • 0 in reply to Vaibhav Jain
    TI__Mastermind 23550 points

    Hi Vaibhav,

    Yes, I can send a configuration file for you next week as I would like to verify it myself prior to sending out. Yes, the configuration file is an option on the last tab of the DAC EVM GUI. Stay tuned!

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 180 points

    Thanks a lot for your help in this regards, Chase. Looking forward to have a go with the config file Slight smile

  • 0 in reply to Vaibhav Jain
    TI__Mastermind 23550 points

    Hi Vaibhav, 

    Please find configuration and instructions attached. I have tested this by modifying our EVM to accept an external OSC input which I have supplied a 100MHz tone.

    DAC39J84EVM_OSC_100MHz_1500MSPS_LMFS4421.pptx

    DAC39J84EVM_100MHz_OSC_input_4421_1500MSPS.cfg

    Regards, Chase