Hello dear community.
I am going to use the AFE58JD32LP and (since the design is almost finished) in short of SPI connections
The AFE has it's own designated SPI bus (1:1 with the FPGA), so I thought that I don't need to use the SEN line and just tie it to GND (through a resistor).
Also, there are not much pins to spare, as the AFE is located on another board then the FPGA.
Now I see some troubling notes on the Data sheet, that defines some timings constraints between SEN and SPI_SCLK, so I reach out seeking an answer.
Will it still work with the SEN tied constantly low?
Thanks
Gady
