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ADC32RF54: Output data rate at x4 averaging

Semion Nemirovsky
Prodigy 40 points
Part Number: ADC32RF54
Other Parts Discussed in Thread: ADC32RF55

Hello!

I have a question about maximum data rates at various averaging settings for the ADC32RF54.

The datasheet states that the sampling rate is limited to 2.6GSPS if x2 averaging is used, in the Electrical Characteristics chapter. And in the JESD204B chapter, it says that for x2 and above, the output format is 16 bits instead of 12.

What I am wondering is - is there any effect on the data rate when using x4 averaging, either in the actual sample rate that I can get on the ADC's output, or in the bit rate of the data lanes. And following this - is there any disadvantage at all for using x4 versus x2, other than the increased power consumption and layout complexity.

  • +1
    TI__Mastermind 20865 points

    Hi Semion,

    Correct, the output changes from 14 bit to 16 bit. The 12 bit output is only applicable to the ADC32RF55 (3 GSPS) device in bypass mode using 8-2-8-20, which will become active online in the next few weeks. The device on your EVM is a 2.6 GSPS device.

    Increased power consumption, routing complexity, and increased drive level are the downsides for 4x averaging. In averaging modes, the input signal voltage is consistent to both ADC input and add linearly, however the noise only adds by root-sum-square method. Therefore, each 2^N of averaging, the noise is reduced by 3dB*N. In 4x averaging, the noise should improve by roughly 6dB when compared to 1x averaging. The analog input bandwidth is comparable however the shape of the frequency response may be slightly different. The roll off may be a few 100MHz earlier and the linearity may dip a bit further before peaking as a result of front end matching. This should be the only difference. Calibration and other features such as DDC will remain the same.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 40 points

    Fantastic!

    Our application does not need the full analog bandwidth of this device, so x4 should be the best mode.

  • 0 in reply to Semion Nemirovsky
    TI__Mastermind 20865 points

    Semion,

    I'm not sure if you guys are planning to use any decimation mode either, but if not needing a full Fs/2 instantaneous bandwidth, decimation will improve performance via processing gain. For each 2^N of decimation, the out of band noise is reduced by 1/2^N and the added processing gain will be 3dB * N. Other benefits of decimation modes are reduced output data rate (directly proportional to the decimation factor) as well as a reduced number of JESD lanes. This means routing may become slightly easier due to the JESD lane mapping MUX which I mentioned this previous weekend via email. You could simply choose the most favorable JESD lanes to route if not planning to use DDC bypass mode.

    Thanks

  • 0 in reply to Chase W
    Prodigy 40 points

    We do need the full 2.4GSPS sample rate, so ADC-based decimation is impossible.

    Later down the line we will sometimes use it in the FPGA.

    Other than using the MUX or the FPGA's ability to swap lane polarity, we will have to route all lanes.

  • 0 in reply to Semion Nemirovsky
    TI__Mastermind 20865 points

    Sure, that is fine.

    With all lanes routed, there will be no issue testing out decimation modes down the line so you can offload some processing from the FPGA to the ADC if you desire.

    What is the max signal bandwidth/range that is restricting you to bypass mode at 1.2GHz IBW? The lowest decimation this part can do is /4 so 300MHz would be the new IBW. If the signal is within 300MHz, you can still sample at 2.4 GSPS but just send 300MHz worth of data instead of 1.2GHz worth of data and still reach any 300MHz window up to Fs/2 using the NCO. Just wanted to provide some extra info as for many I have spoken with this is the first time encountering decimation in our ADCs.

    Regards

  • 0 in reply to Chase W
    Prodigy 40 points

    The application is fairly niche.

    Let's continue this by e-mail.