This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7066: Question about driving ads7066

Part Number: ADS7066
Other Parts Discussed in Thread: ADS8168, OPA325

Hi,

I have an amplifier (non-TI) with a GBW of 1MHz om the front emd used to drive the ADC, and am getting a little mixed up about the external RC required to drive the input of the 7066.   This particular amplifier will have a non-inverting linear gain of 125 and about 50 ohms output impedance.   I calculate an acquisition time of around 100us based on a final sample rate of 10kHz (sample time + conversion time), and come up with a R value of above 4.7kohms  minimum, and a C of 620pF nominal.   Does this make sense for optimal drive circuit values?    Using the analog engineer's design guide, the sample rate used suggests that the min GBW of the amplifier should be under 100kHz, which seems miraculously low.    Am I missing something, and are there any other 16 bit, 8 channel converters that don't require a front end RC at a similar size/cost?   The application is a portable EEG system, and we are looking for an ADC that will fit up well with minimum external component requirements.

Thanks!

  • Jordan,

    Selecting the correct RC filter and amplifier bandwidth can be a challenging problem to solve.  We have a video series that covers the subject: sar-adc-front-end-component-selection.  Long story short, we usually like to simulate the circuit to be confidant that it is settling properly.  In your case, having a long acquisition makes it easy to settle as the time available is relatively long.  I will run a simulation for your example on Monday morning with a TI 1MHz bandwidth amplifier. 

    Regarding other options:  In general, it is useful to have an external RC circuit after the amplifier from a noise perspective. The ADS8168 is a 16 bit converter similar to 7066.  I can simulate the circuit without any RC circuit, and see if it settles.  Considering that your acquisition time is fairly long I think it is likely you could skip the RC circuit.  Of course, you may see more noise without the filter.

    I'll send you an update on Monday morning.

    Art

  • Art, that would be fantastic.  Im not super familiar with TINA, so your help is much appreciated.    I can share more information on the front end amplifier if required.  Thanks!!!

  • Jordan,

    Below is the simulation results and attached is the TINA file.  I used my own custom model, as we are in the process of updating all the ADC models and the new model topology is more accurate.  Of course, this only gives a rough idea of what to expect as I selected a 1MHz TI amplifier that doesn't match your amp.  I would say that you need to be careful about the amplifier and its output impedance.  You mentioned that the output impedance is 50 ohms.  Is this open or closed loop output impedance?  I simulated with an amplifier with a bandwidth of 1MHz and an open loop output impedance of 2300.  This is pretty high.  This amplifier settled wo an error of about -30uV.  You can see the settling is slow, but the acquisition time is very long so it works out.  If you want to use a TI amplifier I can easily verify the settling.  If not, you may use one with a slightly wider bandwidth or a low output impedance (50 ohms is pretty good if it is the open loop spec).  The reason for the concern is that the gain of 125 effectively reduces the bandwidth.  Also, if the output impedance is high this will slow down the charging of the sample and hold.  Bottom line is that you are very likely going to get good settling because your acquisition period is long but there is some possibility that you will have settling errors.   You also should not need the typical RC filter although this may impact your noise performance somewhat.  Let me know if you need additional details.

    In the figure below the key things to look at are the acquisition time, conversion time, amplifier settling, and ADC settling.  Note that the amplifier+ADC settles fairly slowly, but that is ok as the acquisition time is long.  Nevertheless, personally, I would like faster settling than this.  Note that the EVM for this device has one channel with an op amp (opa325 10MHz amp).  You could desolder this amplifier and test you amplifier / gain configuration with the hardware EVM.

      

    ads7066.TSC

  • Hi Art,

    Thanks a lot for the information - The closed loop output impedance of the amplifier is around 1kohm at 10kHz, and goes down (approximately 100 ohms/decade).  We have a 50 ohm resistor in series with the output, as it is recommended to add some resistance at the output to ensure phase margin stability when driving load with parasitic capacitance.    So, I am stuck with this particular amplifier for now - With the 8168, it looks like I could skip the RC charge bucket on the front end, and use a single op-amp buffer to drive the ADC after the MUX.   Unfortunately, it looks like that amplifier is unavailable, so I will stay with the 7066.   In that case, should I use the calculated RC filter I described below, or would it just be better to measure with/without?

  • Jordan,

    Since you need the 50 ohm resistor for good phase margin, then you will definitely need to add that. I think it is likely that you will not need an external capacitance, but if you can afford the space I would add a place holder for the capacitance.  A typical value for this capacitance ranges from 100pF to 1nF.  If you choose a TI equivalent amplifier I can confirm this in simulation.  Alternatively, you could purchase the EVM and test to make sure you get good settling.  Finally, you could choose an amplifier with a wider bandwidth and lower output impedance for some additional design margin.  From my simulations, I think there isn't a lot of margin for a 1MHz bandwidth amplifier in a gain of 125 (and with somewhat high output impedance).  Sorry that I am not more definitive, but without a simulation model and a somewhat marginal set of conditions it is hard to be certain.  

    Art