Part Number: DAC5681Z
I inherited some code from another project.
It is intended to output a waveform from FPGA memory with a 60MHz frequency. I know the memory contents were tested using the dev board for this DAC, so I am not concerned about them.
The code I have is outputting the data directly at a rate of 250MHz. No SERDES blocks are used. It is also driving the DCLK and CLK_IN both at 250MHz.
I checked and only CONFIG register 1 is changed, the interpolation is shut off. All other settings are default.
The output I am getting from the DAC though, instead of 60MHz, is roughly 42.5 MHz
Can anyone shed some light on why this is happening and how I might fix it?
