Other Parts Discussed in Thread: ADS127L11, ADS127L01
Hi,
My customer is dealing with the design of an acquisition card that uses the TI ADS1271 component.
Reading the datasheet it is reported that in the Frame Sync operating mode the CLK and SCLK must respect a specific relationship. Based on tables 10 and 11 it can be deduced that the frequency ratio must be 4 or 8 in the Low-Power mode we use. Looking at the ADS1271EVM eval board I realized that in Frame Sync mode the SCLK is a copy of CLK not respecting the timing described in the datasheet.
Is it possible to clarify if in the aforementioned mode we can use the ADC with the same signal on CLK and SCLK or is it necessary to respect the ratio of 4 or 8?
Thank you.,
Antonio