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Original question:

DAC39J84EVM: change/add reference clock to work in combination with ADC12DJ3200

DAC39J84EVM: Unable to replicate the pattern sent from DAC on ADC/Oscilloscope and ways to achieve integer sampling rate

Vaibhav Jain
Prodigy 180 points
Part Number: DAC39J84EVM
Other Parts Discussed in Thread: ADC12DJ3200, DAC39J84, LMK04828

Hi All,

We are sending a pattern ( screenshot attached ) which has a peak at 25 MHz and a wideband with central frequency at 200 MHz as shown in the screenshot using DAC39J84EVM with the DAC settings as shown in the figure attached. The pattern is sent to the DAC by loading an external pattern file (.csv format) on the GUI and the file is attached as well for reference. We send this pattern directly to the ADC12DJ3200 by connecting SMA fibre directly from DAC to the input channel of ADC. The observed frequency spectrum and time domain codes from the ADC are as shown in the figures below.  The .csv file of the output time domain are attached as well. The expected output on ADC should have been the pattern sent from the DAC, however there is a marked discrepancy between the two. We checked the output of the DAC on a spectrum analyser and an oscilloscope as well, which shows the same result as ADC, pointing to the fact that the output from DAC is not as is being sent and shown on DAC GUI. Could there be any specific reason for this? 

Also, regarding the sampling rate of DAC, which is 2.8GSPS, but when entering through GUI, we are able to access a maximum of 1228.8 MSPS (DAC Data Input rate), how can we access full sampling rate of DAC. Also, is there a way to make the DAC data input rate as 1 GSPS or some integer value as that would be very convenient to our experiment? What changes would we need to do for the same and is this the reason why we are getting such results on ADC ( DAC not being able to sample at 1 GSPS)?

Thanks for your consideration and looking forward to your response. Slight smile

DAC settingsTime domain and frequency spectrum (sent from DAC))I and Q signals RRC filter.csvoutput frequency spectrum from ADCoutput from ADC time domainFaulty_Pattern_Recieved.csv

  • 0
    TI__Mastermind 20835 points

    Hi Vaibhav,
    As you can see in the first image, the DAC is outputting an average code swing of around 10 codes due to the nature of this wideband signal. This will be tough to pickup on the ADC or oscilloscope and requires a high dynamic range device with a very low noise floor. First, can you repeat the test with a single tone DAC output? This will confirm that the DAC is configured properly for this operating mode.

    Regarding the DAC sample rate, at 1x interpolation, the maximum sample rate for this DAC shows as 1250MSPS. This is due to the 12.5Gbps serdes limitation for the JESD204B interface. In order to sample at higher frequencies, some interpolation is required, which will reduce the IBW for the DAC. Please refer to Table 11. DAC39J84 Speed Limits of the DAC39J84 datasheet to see a breakdown of serdes rates vs interpolation vs number of JESD lanes.

    Unfortunately, it will not be possible to achieve a sample rate which is a rounded number in GSPS while using the onboard clock (and/or without modifications). This EVM has a 122.88MHz crystal oscillator reference to the LMK04828 PLL2 which is the synthesized clock output. Unless you are willing to swap this 122.88MHz crystal oscillator to a 100MHz crystal oscillator, the only other option to achieve this will be to modify the EVM for an external PLL reference by removing the JP2 jumper, remove C82, remove R177, populate R185, populate R186, populate C92. This will allow the signal from J17 to act as an external PLL reference which you can supply 100MHz. This has no affect on the results you are seeing at the ADC. 

    Regards, Chase