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ADS42LB69: How to change ADC sampling rate.

Ajay Lamani
Prodigy 10 points
Part Number: ADS42LB69

I'm working on project  where I'm using ADC(ADS42LB69),16bit.

I wanted to know how to change the sampling rate of the ADC, as per spec Min is 10MSPS and Max is 250 MSPS. And the input clock frequency used in my project is 50Mhz. So, how can I change the sampling rate of ADC by keeping my input clock frequency to 50Mhz.

So please can you let me know, how to go ahead.

  • 0
    TI__Mastermind 23750 points

    Hi Ajay,

    This device does not contain an on-chip PLL so in order to achieve a faster sampling rate, you simply must increase the input sample clock to the ADC. You can reduce the sample rate by either decreasing the sample clock or by utilizing the internal clock divider function. This function allows for divide-by-1, divide-by-2, or divide-by-4 modes and will reduce the applied sampling clock by the selected amount based upon the value in register 0x06. This function is meant to be used in systems where an existing sample clock exceeds the maximum sample clock for this device, however there is no reason it should not allow for a 25MHz clock or a 12.5MHz clock in your case. Please refer to section 8.6.1.1 Register 6 (offset = 06h) [reset = 80h] for the clock divider settings.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Thanks chase,

    I will try to go ahead with the above solution recommend.