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ADS127L11: How to interface this AD to uC that uses only I2S SPI mode

Part Number: ADS127L11
Other Parts Discussed in Thread: ADS1672, , ADS127L01, ADS1274, ADS1271

Using ADS127L11 to replace previously used ADS1672 A/D. Previous part used I2S audio SPI mode which combined the functions of CS with DRDY on same pin called FSYNC. I2S mode slave select (SS) pin of uC connected to A/D FSYNC pin. But ADS127L11 uses two pins, DRDY out to signal uC to synchronize, and CS input to intiate data read. Total of pins 5: SDI, SDO, SCK, CS, DRDY.

Possible to use "3-wire" mode which holds CS low, to interface to uC using SPI with only SDI, SDO, SCK, SS. CS is held low to enter "3-wire" mode. But must set CS high to program ADS127L11 register for external clock, but that switches part into 4-wire mode (5 pins). ADS127L11 does not send data unless CS is set high and low in "4-wire" mode. But SS pin of uC watches the DRDY pin of AD, is not available to control AD CS pin.

Only way to enter 3 wire mode is hold CS low on reset or powerup, but then lose register settings for external clock. So cannot use 3-wire mode or 4-wire mode.

High speed application uses DMA to transfer SPI data to memory. Cannot use processor to hang out to bit-bang 5th pin.

uC is PIC32MZ0512EFE064

  • Edit: ADS1672 functioned with CS pin held low. uC interfaced to DRDY pin. ADS127L11 only works with CS low in 3-wire mode, which cannot program register for external clock.

  • Hello Garrick,

    Both primary and secondary support engineer for those ADCs are on vacation because of Christmas holiday, please allow a response delay from them. Thanks.

    Best regards,

    Dale 

  • Hello Garrick,

    The ADS127L11 is intended to be used with SPI port, 3 or 4 wire, with DRDY pin monitored by processor interrupt.  I am not sure if you can get the interface to work with a standard audio I2S interface, but if the I2S port on your processor has enough configuration flexibility, it may be possible. 

    However, you can write to the internal registers in 3-wire mode.  On power-up/reset, the device defaults to a 24b output word, with no CRC or Status.  In order to write to an internal register, pad the MSB with zeroes.  

    As an example, in order to configure the ADS127L11 to use external clock after power-up, write the following 24 bit command (compatible with 3-wire or 4-wire mode).

    0x00 88 80h

    Another option may be to consider using the ADS127L01.  This is the previous generation of the ADS127L11, and supports frame-sync mode.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Keith,

    I preferred the ADS127L01 because it has serial operation like the ADS1672. But the ADS127L11 is all that was in stock that would be compatible in performance. When I previously found an AD in stock, by the time I got one and I tested it, stock of that part disappeared world wide. So we grabbed this part when it appeared at a distributor.

    I have a PCB designed and ready to order with some logic added that creates a long CS signal by counting clocks, but I still want to save chips if I can.

    It my testing it seemed if the CS pin was taken high after power-up, then it was in 4 wire mode until it was reset again. Correct?

    In the datasheet, "After the ADC is powered up or reset, the default output frame size is 24 bits. In 3-wire SPI mode, the input frame must match the size of the output frame for the SPI to remain synchronized."

    If the CS held low, what is used to synchronize the 24-bit frame to input data to the AD? Is START set high so that the DRDY pin (400 kHz) signals the uC when to start sending 24 bit frames to the AD?

  • Hello Garrick,

    Yes, if /CS is taken high after power-up, then the ADS127L11 will go into 4-wire SPI mode and stay in that mode until reset again, including power-up reset.

    The typical configuration for 3-wire mode is to permanently connect /CS to ground.  After reset, the ADS127L11 uses an internal counter to keep track of the frame.  Since the ADC frame size after reset is 24b, it will count the number of SCLKs input to the ADC and after the 24th SCLK, it will treat this as the end of the first frame (same behavior in 4-wire mode when /CS is pulled high).  The ADC will then count the next 24 SCLKs (total of 48 after reset) and treat this as the second frame, and so forth.

    After power-up, the host processor can send multiple 24b frames to configure the internal registers, and then monitor the DRDY line to align to the conversion complete.  The START pin can be held high for continuous conversion, which is the mode I think you need if you are going to get I2S to work.  Yes, START needs to be set high so that the ADC will generate a DRDY signal, which is 400kHz with default reset values.

    Regards,
    Keith

  • Your explanation very clear. The next datasheet revision should incorporate it. It seems the uC PIC32MZ SPI module is not able to be configured for this. The frame mode can be either 64 or 32 bit, not 24. I could send 3 bytes in sequence but non-framed mode does not permit combined setting of SPI as Master with CS as slave input to be triggered by the AD DRDY pin. Therefore I have to use the AD in 4-wire mode to configure and then must continue using 4-wire for data retrieval in AD running mode. 

  • Hello Garrick,

    If using 3-wire mode, then you need to start with 24b frames.  You can change this to 32b frames by enabling the Status word.  In this case, you would pad 16 leading bits on SDI with zeroes, followed by the 16b command word.  The SDO would include the 8b status word followed by the 24b conversion result.

    The other option is to use a different ADC that supports frame-sync mode.  I had mentioned the ADS127L01, which does appear to have limited stock.  Another ADC option is the ADS1271 (single channel) or ADS1274 (quad channel).

    Regards,
    Keith