• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 334 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS124S08: Question about START Command Operation

Darren (FAE)
Expert 5483 points
Part Number: ADS124S08


I am supporting an applicatiion where ADS124S08 will be controlled mainly through SPI commands.
One topic of concern relates to the START command.

Consider a use-case where xRESET is pulled HIGH.
In this case, an SPI write sending the RESET command is needed to RESET the device.

This is a fairly open-ended question, but could there be a situation where the ADS124S08 doesn't respond to the START command?
(i.e. maybe there is transient burst noise at the inputs, or ESD event, etc that causes latch-up or results in the serial communication path not functioning?)

Regards,
Darren

  • 0
    TI__Guru 53256 points

    Hi Darren,

    The short answer is yes, it is possible for the events you described to cause the serial interface to become unresponsive. In this case, any command might not be recognized by the ADC. This is why there we generally include a dedicated RESET pin, for just such an event.

    In your case where only commands are being used and none of the dedicated pins (RESET, START) are controllable, the only way to recover the ADC would be to power cycle the device.

    -Bryan

  • 0 in reply to Bryan Lizon86
    TI__Expert 5483 points

    Hi Bryan,

    Thanks for the feedback. I have a follow-up.

    Are there any rise/fall time requirements for the xSTART pin?
    Can an edge be "too fast" or "too slow"?

    To reduce the chance of noise getting onto the xSTART pin and triggering the device, 
    what would be your thoughts on adding an RC filter into this pin? (It could slow the signal edge somewhat)

    Regards,
    Darren

  • 0 in reply to Darren (FAE)
    TI__Guru** 113765 points

    Hi Darren,

    Bryan was helping me out while I was out of office (thanks Bryan!)  A couple of things to consider:

    • Using CS will reset the SPI bus at the start of the communication.  If you are able to control CS, the previous communication will reset once CS goes back high.  This will allow the command to be repeated if the previous communication failed.
    • If CS is pulled low continuously, enabling the SPI timeout will reset the SPI communication following the timeout period.  The timeout feature is enabled by setting the TIMEOUT bit to 1 in the system control register (09h).

    If you use the START command instead of the START pin, then the START pin should be connected to DGND.  In this case I'm not sure how adding an RC to the pin would help.

    As to when the START pin triggers, this will depend on the Vih logic high value as given in the datasheet which is 0.7*IOVDD for a logic high (and 0.3*IOVDD for Vil logic low).  Figure 4 in the datasheet shows the required pulse width of 4*tCLK (just under 1us) before the conversion will start.  So any noise on the START pin would need to be equal to or greater than Vih for 1us for the conversion to start.  Here you can see that connecting the START pin directly to DGND would not allow this pin to go to Vih.

    If the START pin is controlled, then adding some sort of filtering may be desired or even required.  In this case instead of using an RC I would recommend something like the Murata feed-through EMI filter capacitor NFM18CC101R1C3D.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    TI__Expert 5483 points

    Hi Bob,

    I appreciate the comment.
    Can you just confirm for me if the RESET pin has a required input slew rate? (tr/tf)

    For the RESET pin, what would be an appropriate way to filter noise on this signal?
    The Murata feed-through EMI filter cap is still viable?

    The S21 diagram from the product page shows a single-pole rolloff after ~10MHz.
    Seems like an RC filter would be just as effective at making a single-pole filter...is there a reason you recommend the cap instead? (few parts?)
    To get a similar 10MHz rolloff like that EMI cap, a 10Ω / 2.2nF RC filter seems like it would do the job just as well...?

  • 0 in reply to Darren (FAE)
    TI__Guru** 113765 points

    Hi Darren,

    The voltage requirements on the digital pins are specified as Vih and Vil where the state must be held long enough for the ADC to recognize the desired action. The pins are not tested for slew rate.  The digital action is when the pin is at Vil or below, the device action is logic low.  If the voltage rises on the pin, the action doesn't change until Vih is reached.

    I've only seen a series RC (power to ground) with the cap on the ground side and the junction of the resistor/cap connected to the RESET pin.  The design is meant to delay the release of the reset on power up.  I have not seen this method used on a controlled signal.  Here you would see a similar response so what you propose would seem feasible.  I still would recommend the feed-through cap due to the construction and extremely low-inductance for shunting high-frequency noise.  You can get larger values than 100pF (which is what I mentioned previously) if you want different characteristics of the filtering.

    All that said, in general you don't want to have slow moving signals on CMOS digital inputs.  Consider that CMOS is a stacked set of PMOS and NMOS transistors and at some point there is a crossover region where both transistors will conduct.  If this period is long, then conduction of current can be quite high for the crossover duration.

    Best regards,

    Bob B