Hello,
I have two questions reguarding the sampling clock phase adjust feature on the ADC12d1620QML-SP. In the data sheet it mentions the following...
"The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature helps the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase-array antennas"
Question 1:
Does the phase adjust refer to the individual data clock outputs (i.e DId0+/-) having the phase adjust to correct for small imbalances or is it that the phase adjust corrects delay on each net of the bus and you cannot isolate individual data clock ouputs such as the DId0+/-? Is the small imbalances referring to the event that a board designer did not phase match the nets correctly, which is where having the ability to phase adjust things could help?
Question 2:
From an implementation standpoint can I get away with justonly using the Data clock output for the I- and Q-channel data bus and not using the delayed ones? I am working on a board design with limited space so less is more and having to only route non-delayed data clock outputs would make things easier from an implementation point of view.
Thanks,
Mickel
