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The datasheet is described as follows:
DACx0508C. A low value on the CLR pin causes the DAC outputs of those channels
configured for clear operation to update their registers and output to the reset value: zero
scale (DACx0508Z) or midscale (DACx0508M). Bringing the CLR pin high causes the
device to exit clear mode.
For DAC80508ZC(CLR pin and zero scale during reset:),CH0 is configured to output the reset value of 0 when the CLR pin is low.
first the value of CH0 data register(DAC0-DATA) is 0x2000,
then the CLR pin changes from high to low,CH0 output about zero voltage, what is the value of DAC0-DATA,0 or 0x2000?
at last the CLR pin changes from low to high,what is the value of DAC0-DATA,0 or 0x2000?
Hi,
Ater CLR pin goes from high to low, both buffer and active registers of the specific channel (in this case CH0) is cleared. Meaning DAC_DATA registers will be 0x0000.
Even if you bring CLR pin low to high after the above scenario, DAC_DATA registers will be 0x0000.
Hope this helps
Regards,
AK
Thanks! In fact, what I need is to temporarily reset the output to 0 by setting the CLR low, and restore the original value by setting the CLR high!
Hi Andy,
Just something to think about.
We have some devices like the DAC63204 that have a GPI pin that can be configured to power up/down the outputs. That sounds more like the behavior you're looking for. The output will be shut down to either 0V or hi-z (depending on the setting) when the GPI is low, and then it'll return to the value stored in DAC-DATA when the GPI is high. The max channel count/resolution is 4-ch/12-bit though.
Best,
Katlynne Jones