Hello all,
I work with the ADS5294 (own FMC board) and use timing diagram according to
Figure 4. Enlarged 1-Wire LVDS Timing Diagram (14 bit)
from DataSheet.
My FPGA project was based on dedicated deserializer ISERDESE2 of Xilinx FPGA XC7K350T.
Signals Frame Clock, Bit Clock and Output Data have no internal adjstable delays within FPGA.
Clock sourse for ADC was implemented on AD9512 installed on FMC board.
Fsample = Fin/2, so Fsample has duty cycle = 50%.
ADC works stable with the external clock Fsample = 45...50 MHz.
Program gives stable result on RAMP test within this range of Fsample
and gives error below than 45 MHz and higher than 50 MHz.
I set all available values of PHASE_DDR (Figure 58. Phase Programmability Modes for LCLK),
i.e. I set values 0x00, 0x20, 0x40, 0x60 into register 0x42 and I gave absolutely the same result.
It seams as strange result.
Please explain me, why do the value of the PHASE_DDR does not affect the operation of the ADC ?
Thank you,
Best regards,
Viktor
